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Difference between revisions of "MCST/elbrus-4s"
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| clock min = | | clock min = | ||
| clock max = 800 MHz | | clock max = 800 MHz | ||
| − | | package = | + | | package = HFCBGA 1600<ref>https://zoom.cnews.ru/publication/item/51620</ref> |
| − | | socket = | + | | socket = Surface mount |
| − | | succession = | + | | succession = Yes |
| − | | predecessor = | + | | predecessor = Elbrus-2S+ |
| − | | predecessor link = | + | | predecessor link = MCST/elbrus-2s+ |
| − | | successor = | + | | successor = Elbrus-8S |
| − | | successor link = | + | | successor link = MCST/elbrus-8s |
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== Overview == | == Overview == | ||
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The «Elbrus-4S» processor contains 4 cores, level 2 cache memory with a total capacity of 8 megabytes, 3 memory controllers compliant with DDR3-1600, 3 interprocessor communication channels and an input-output channel. Each processor core executes 23 instructions per cycle. The processor contains hardware support for binary translation of 64-bit [[Intel]]/[[AMD]] codes. The average power dissipation is 45 watts. The microprocessor is intended for use in personal computers and servers<ref>http://www.mcst.ru/mikroprocessor-elbrus4s-gotov-k-serijnomu-proizvodtstvu</ref><ref>http://www.mcst.ru/mikroprocessor-elbrus4s</ref>. | The «Elbrus-4S» processor contains 4 cores, level 2 cache memory with a total capacity of 8 megabytes, 3 memory controllers compliant with DDR3-1600, 3 interprocessor communication channels and an input-output channel. Each processor core executes 23 instructions per cycle. The processor contains hardware support for binary translation of 64-bit [[Intel]]/[[AMD]] codes. The average power dissipation is 45 watts. The microprocessor is intended for use in personal computers and servers<ref>http://www.mcst.ru/mikroprocessor-elbrus4s-gotov-k-serijnomu-proizvodtstvu</ref><ref>http://www.mcst.ru/mikroprocessor-elbrus4s</ref>. | ||
Revision as of 06:03, 10 November 2019
| Elbrus-4S | |
| |
| Developer | MCST |
| Type | Microprocessors |
| Introduction | 2014 (launch) |
| Architecture | Elbrus (VLIW) |
| Word size | 64 bit 8 octets
16 nibbles |
| Process | 65 nm 0.065 μm
6.5e-5 mm |
| Package | HFCBGA 1600'"`UNIQ--ref-00000000-QINU`"' |
| Socket | Surface mount |
| Succession | |
| ← | → |
| Elbrus-2S+ | Elbrus-8S |
Elbrus-4S (rus. Эльбрус-4С, code designation: 1891ВМ8Я) is an universal multi-core VLIW microprocessor with the Elbrus architecture, developed by the russian company MCST.
Overview
The «Elbrus-4S» processor contains 4 cores, level 2 cache memory with a total capacity of 8 megabytes, 3 memory controllers compliant with DDR3-1600, 3 interprocessor communication channels and an input-output channel. Each processor core executes 23 instructions per cycle. The processor contains hardware support for binary translation of 64-bit Intel/AMD codes. The average power dissipation is 45 watts. The microprocessor is intended for use in personal computers and servers[2][3].
References
Facts about "MCST/elbrus-4s"
| designer | MCST + |
| first launched | 2014 + |
| full page name | MCST/elbrus-4s + |
| instance of | microprocessor family + |
| main designer | MCST + |
| name | Elbrus-4S + |
| process | 65 nm (0.065 μm, 6.5e-5 mm) + |
| word size | 64 bit (8 octets, 16 nibbles) + |