From WikiChip
Difference between revisions of "Talk:intel/microarchitectures/spring hill"
< Talk:intel‎ | microarchitectures

(Posing a question)
Line 1: Line 1:
 +
{{talk header}}
 +
 +
== 2 chips ==
 
Any idea how the circuits are partitioned across the two chips shown in the package on the M.2 module? [[Special:Contributions/82.102.30.46|82.102.30.46]] 14:05, 21 October 2019 (EDT)
 
Any idea how the circuits are partitioned across the two chips shown in the package on the M.2 module? [[Special:Contributions/82.102.30.46|82.102.30.46]] 14:05, 21 October 2019 (EDT)
 +
 +
:Spring Hill is a single die SoC. The second die on the package is actually the chipset and Intel confirmed it's the same {{intel|ice lake (client)#PCH|PCH as Ice Lake|l=arch}}. I added that information to the article. --[[User:David|David]] ([[User talk:David|talk]]) 04:50, 22 October 2019 (EDT)

Revision as of 03:50, 22 October 2019

This is the discussion page for the intel/microarchitectures/spring hill page.

2 chips

Any idea how the circuits are partitioned across the two chips shown in the package on the M.2 module? 82.102.30.46 14:05, 21 October 2019 (EDT)

Spring Hill is a single die SoC. The second die on the package is actually the chipset and Intel confirmed it's the same PCH as Ice Lake. I added that information to the article. --David (talk) 04:50, 22 October 2019 (EDT)
Retrieved from "https://en.wikichip.org/w/index.php?title=Talk:intel/microarchitectures/spring_hill&oldid=94150"