Semiconductor & Computer Engineering
-
WikiChip
WikiChip
-
Architectures
Popular x86
-
Intel
- Client
- Server
- Big Cores
- Small Cores
-
AMD
Popular ARM
-
ARM
- Server
- Big
- Little
-
Cavium
-
Samsung
-
-
Chips
Popular Families
-
Ampere
-
Apple
-
Cavium
-
HiSilicon
-
MediaTek
-
NXP
-
Qualcomm
-
Renesas
-
Samsung
-
From WikiChip
Difference between revisions of "supercomputers/nersc-10"
| Line 3: | Line 3: | ||
|name=NERSC-10 | |name=NERSC-10 | ||
|image=nersc-10.png | |image=nersc-10.png | ||
| + | |peak dpflops=1 exaFLOPS | ||
|predecessor=Perlmutter | |predecessor=Perlmutter | ||
|predecessor link=supercomputers/nersc-9 | |predecessor link=supercomputers/nersc-9 | ||
Revision as of 01:18, 5 February 2019
| Edit Values | |
| NERSC-10 | |
 | |
| General Info | |
| Peak FLOPS | 1 exaFLOPS |
| Succession | |
NERSC-10 (no name given yet) is the successor to Perlmutter, a planned exascale supercomputer set to be operated by National Energy Research Scientific Computing Center.
Overview
NERSC-10 is a planned exascale supercomputer currently in pathfinding stages. NERSC-10 is expected to go online around the 2024 timeframe.
