Semiconductor & Computer Engineering
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| − | {{title|Chip-on-Wafer-on-Substrate (CoWoS) | + | {{title|Chip-on-Wafer-on-Substrate (CoWoS)}}{{packaging}} |
'''Chip-on-Wafer-on-Substrate''' ('''CoWoS''') is a [[two-point-five dimensional integrated circuit]] (2.5D IC) [[through-silicon via]] (TSV) [[interposer]]-based packaging technology designed by [[TSMC]]. | '''Chip-on-Wafer-on-Substrate''' ('''CoWoS''') is a [[two-point-five dimensional integrated circuit]] (2.5D IC) [[through-silicon via]] (TSV) [[interposer]]-based packaging technology designed by [[TSMC]]. | ||
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| + | == Overview == | ||
| + | CoWoS is a wafer-level [[chiplet|multi-chip]] [[packaging technology]] that incorporates multiple chips side-by-side on a [[silicon interposer]] in order to achieve better interconnect density and performance. The chiplets are bonded through [[micro-bumps]] on a silicon interposer forming a chip-on-wafer (CoW). The CoW is then subsequently thinned such that the [[TSV]] perforations are exposed. This is followed [[C4 bumps]] formation and [[singulation]]. A CoWoS package is completed thrugh bonding to a package substrate. | ||
Revision as of 00:53, 11 January 2019
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Chip-on-Wafer-on-Substrate (CoWoS) is a two-point-five dimensional integrated circuit (2.5D IC) through-silicon via (TSV) interposer-based packaging technology designed by TSMC.
Overview
CoWoS is a wafer-level multi-chip packaging technology that incorporates multiple chips side-by-side on a silicon interposer in order to achieve better interconnect density and performance. The chiplets are bonded through micro-bumps on a silicon interposer forming a chip-on-wafer (CoW). The CoW is then subsequently thinned such that the TSV perforations are exposed. This is followed C4 bumps formation and singulation. A CoWoS package is completed thrugh bonding to a package substrate.