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Difference between revisions of "arm holdings/microarchitectures/cortex-a73"
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| [[GCC]] || <code>-mtune=cortex-a73.cortex-a53</code> | | [[GCC]] || <code>-mtune=cortex-a73.cortex-a53</code> | ||
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| + | == Architecture == | ||
| + | === Key changes from {{\\|Cortex-A72}} === | ||
| + | {{empty section}} | ||
Revision as of 13:52, 31 December 2018
| Edit Values | |
| Cortex-A73 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | May 29, 2016 |
| Instructions | |
| ISA | ARMv8 |
| Succession | |
Cortex-A73 (codename Artemis) is the successor to the Cortex-A72, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A73, which implemented the ARMv8 ISA, is the a performant core which is often combined with a number of lower power cores (e.g. Cortex-A53) in a big.LITTLE configuration to achieve better energy/performance.
Compiler support
| Compiler | Arch-Specific | Arch-Favorable |
|---|---|---|
| Arm Compiler | -mcpu=cortex-a73 |
-mtune=cortex-a73
|
| GCC | -mcpu=cortex-a73 |
-mtune=cortex-a73
|
| LLVM | -mcpu=cortex-a73 |
-mtune=cortex-a73
|
If the Cortex-A73 is coupled with the Cortex-A53 in a big.LITTLE system, GCC also supports the following option:
| Compiler | Tune |
|---|---|
| GCC | -mtune=cortex-a73.cortex-a53
|
Architecture
Key changes from Cortex-A72
 |
This section is empty; you can help add the missing info by editing this page. |
Facts about "Cortex-A73 - Microarchitectures - ARM"
| codename | Cortex-A73 + |
| designer | ARM Holdings + |
| first launched | May 29, 2016 + |
| full page name | arm holdings/microarchitectures/cortex-a73 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Cortex-A73 + |