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Difference between revisions of "arm holdings/microarchitectures/arm9"
< arm holdings

(Die)
(process technology)
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=== 0.13 μm ===
 
=== 0.13 μm ===
 
==== ARM926EJ-S ====
 
==== ARM926EJ-S ====
* [[0.13 μm process]]
+
* [[0.20 μm process]]
 
* 3.2 mm² die size (with cache)
 
* 3.2 mm² die size (with cache)
 
* 1.68 mm² die size (without cache)
 
* 1.68 mm² die size (without cache)

Revision as of 02:44, 9 October 2020

Edit Values
ARM9 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerVLSI Technology, TSMC
IntroductionOctober 16, 1997
Succession

ARM9 is the successor to the ARM8, a low-power performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as an IP core and is sold to other semiconductor companies to be implemented in their own chips.

Architecture

Key changes from ARM8

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Block Diagram

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Memory Hierarchy

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Licensees

In 2013 Arm reported 271 licensees. The following were named.

Die

0.35 μm

ARM9TDMI

  • 0.35 μm process
  • 112,000 transistors
  • 4.15 mm² die size
  • 1.8 mW/MHz @ 3.0V
  • 120 MHz max frequency

ARM940T

  • 0.35 μm process
  • 800,000 transistors
  • 13.0 mm² die size
  • 2 x 4 KiB caches
  • 400 mW @ 120 MHz core / 16 MHz bus

0.25 μm

ARM9TDMI

  • 0.25 μm process
  • 3 metal layers
  • 110,000 transistors
  • 4.15 mm² die size
  • 2.5 V
  • 200 MHz max frequency
  • 150 mW

0.18 μm

ARM926EJ-S

  • 0.18 μm process
  • 8.3 mm² die size (with cache)
  • 4.0 mm² die size (without cache)
  • 180-200 MHz max frequency
  • 1.40 mW/MHz with cache
  • 1.00 mW/MHz without cache

0.13 μm

ARM926EJ-S

  • 0.20 μm process
  • 3.2 mm² die size (with cache)
  • 1.68 mm² die size (without cache)
  • 266 MHz max frequency
  • 0.45 mW/MHz with cache
  • 0.30 mW/MHz without cache

Bibliography

codenameARM9 +
designerARM Holdings +
first launchedOctober 16, 1997 +
full page namearm holdings/microarchitectures/arm9 +
instance ofmicroarchitecture +
manufacturerVLSI Technology + and TSMC +
microarchitecture typeCPU +
nameARM9 +