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Difference between revisions of "cavium/thunderx/cn8890"
< cavium‎ | thunderx

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|max memory=1 TiB
 
|max memory=1 TiB
 
}}
 
}}
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== Cache ==
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{{main|cavium/microarchitectures/ThunderX1#Memory_Hierarchy|l1=ThunderX1§ Cache}}
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{{cache size
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|l1 cache=110 KiB/core
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|l1i cache=78 KiB/core
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|l1i desc=39-way set associative
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|l1d cache=32 KiB/core
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|l1d desc=32-way set associative
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|l1d policy=write-back
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|l2 cache=16 MiB/socket
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|l2 desc=16-way set associative
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|l2 policy=write-back
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}}
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ThunderX_CP: public and private cloud servers.
 +
 +
[https://www.cavium.com/pdfFiles/TIRIAS-ThunderX-Memecached-TCO-white-paper.pdf]

Revision as of 22:14, 3 December 2018

Edit Values
ThunderX CN8890
General Info
DesignerCavium
ManufacturerGlobalFoundries
Model NumberCN8890
Part NumberCN8890-1900BG2601-AAP-Y-G
MarketServer
IntroductionJune 3, 2014 (announced)
March 31, 2016 (launched)
Release Price$785
General Specs
FamilyThunderX
Frequency1,900 MHz
Bus typeCCPI
Microarchitecture
ISAARMv8.1 (ARM)
MicroarchitectureThunderX2
Process28 nm
TechnologyCMOS
Word Size64 bit
Cores48
Threads48
Max Memory1 TiB
Multiprocessing
Max SMP2-Way (Multiprocessor)

Cache

Main article: ThunderX1§ Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$110 KiB/core
"KiB/core" is not declared as a valid unit of measurement for this property.
L1I$78 KiB/core
"KiB/core" is not declared as a valid unit of measurement for this property.
 39-way set associative 
L1D$32 KiB/core
"KiB/core" is not declared as a valid unit of measurement for this property.
 32-way set associativewrite-back
L2$16 MiB/socket
"MiB/socket" is not declared as a valid unit of measurement for this property.
   16-way set associativewrite-back

ThunderX_CP: public and private cloud servers.

[1]

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/thunderx/cn8890&oldid=84596"
Facts about "ThunderX CN8890 - Cavium"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
ThunderX CN8890 - Cavium#pcie +
base frequency1,900 MHz (1.9 GHz, 1,900,000 kHz) +
bus typeCCPI +
core count48 +
designerCavium +
familyThunderX +
first announcedJune 3, 2014 +
first launchedMarch 31, 2016 +
full page namecavium/thunderx/cn8890 +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaARMv8.1 +
isa familyARM +
l1$ size5,280 KiB (5,406,720 B, 5.156 MiB) +
l1d$ description32-way set associative +
l1d$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l1i$ description39-way set associative +
l1i$ size3,744 KiB (3,833,856 B, 3.656 MiB) +
l2$ description16-way set associative +
l2$ size16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
ldateMarch 31, 2016 +
manufacturerGlobalFoundries +
market segmentServer +
max cpu count2 +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory channels8 +
max sata ports16 +
max usb ports2 +
microarchitectureThunderX1 +
model numberCN8890 +
nameThunderX CN8890 +
part numberCN8890-1900BG2601-AAP-Y-G +
process28 nm (0.028 μm, 2.8e-5 mm) +
release price$ 785.00 (€ 706.50, £ 635.85, ¥ 81,114.05) +
smp max ways2 +
supported memory typeDDR4-2400 + and DDR3-2133 +
technologyCMOS +
thread count48 +
word size64 bit (8 octets, 16 nibbles) +