Semiconductor & Computer Engineering
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== Bibliography == | == Bibliography == | ||
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* {{hcbib|30}} | * {{hcbib|30}} | ||
[[category:ibm]] | [[category:ibm]] | ||
[[Category:memory subsystem]] | [[Category:memory subsystem]] | ||
Revision as of 22:02, 27 September 2018
Centaur is is a memory buffer chip designed by IBM for their POWER scale-up microprocessors. First introduced with the POWER8 microarchitecture, each Centaur chip includes 16 MiB of eDRAM and four DDR3/DDR4 DRAM ports.
Contents
Overview
Due to the inherent limitations of scaling DDR to a large number of channels, IBM uses an array of SerDes on the POWER die in order to communicate with an intermediate memory buffer chip, called Centaur, which is used to access a larger set of DDR devices. Centaur is fabricated on 22 nm SOI, has 16 MiB of eDRAM, and includes four DDR3/DDR4 ports support 1 DIMM per port.
POWER8 and POWER9 processors that rely on Centaur communicate in a memory-channel-agnostic way. Operations such as cache-line reads/writes are sent to the chip as high-level commands. Scheduling is no longer tightly controlled by the microprocessor as it did in prior designs (e.g., POWER7. It's worth noting that the agnostic attribute of Centaur, new memory technologies (e.g., storage-class memory) can be introduced without any fundamental changes to the microprocessor itself.
Mechanism
Both POWER8 and POWER9 have two memory controllers capable of driving four differential memory interface (DMI) channels, each with a maximum signaling rate of 9.6 GT/s. Each channel provides 2B wide read and 1B wide write for a sustained bandwidth of up to 28.8 GB/s. Each of the DMI channels connects to a dedicated Centaur chip which, in turn, provides four DDR4 memory channels running at up to 3200 MT/s as well as 16 MiB of L4 cache. In other words, with this configuration, a single processor can use eight buffered memory channels to access up to 32 channels of DDR memory. Note that each buffer chip DDR4 port supports a single DDR4 DIMM.
Centaur operates on high-level commands sent from the microprocessor. Requests are handled as quickly as possible. The chip is capable of reordering DRAM requests and since there is a large level 4 cache on-die, requests hitting the cache are sent right away, meaning some requests may be reordered.