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Difference between revisions of "intel/microarchitectures/tremont"
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− | {{intel title|Tremont| | + | {{intel title|Tremont|arch}} |
− | {{microarchitecture}} | + | {{microarchitecture |
+ | |atype=CPU | ||
+ | |name=Tremont | ||
+ | |designer=Intel | ||
+ | |manufacturer=Intel | ||
+ | |introduction=2018/2019 | ||
+ | |type=Superscalar | ||
+ | |oooe=Yes | ||
+ | |speculative=Yes | ||
+ | |renaming=Yes | ||
+ | |isa=x86-64 | ||
+ | |extension=MOVBE | ||
+ | |extension 2=MMX | ||
+ | |extension 3=SSE | ||
+ | |extension 4=SSE2 | ||
+ | |extension 5=SSE3 | ||
+ | |extension 6=SSSE3 | ||
+ | |extension 7=SSE4.1 | ||
+ | |extension 8=SSE4.2 | ||
+ | |extension 9=POPCNT | ||
+ | |extension 10=AES | ||
+ | |extension 11=PCLMUL | ||
+ | |extension 12=RDRND | ||
+ | |extension 13=SHA | ||
+ | |core name=Gemini Lake | ||
+ | |predecessor=Goldmont Plus | ||
+ | |predecessor link=intel/microarchitectures/goldmont plus | ||
+ | }} |
Revision as of 13:56, 4 April 2018
Edit Values | |
Tremont µarch | |
General Info | |
Arch Type | CPU |
Designer | Intel |
Manufacturer | Intel |
Introduction | 2018/2019 |
Pipeline | |
Type | Superscalar |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Instructions | |
ISA | x86-64 |
Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, SHA |
Cores | |
Core Names | Gemini Lake |
Succession | |
Facts about "Tremont - Microarchitectures - Intel"
codename | Tremont + |
designer | Intel + |
first launched | 2019 + |
full page name | intel/microarchitectures/tremont + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Tremont + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |