From WikiChip
Difference between revisions of "intel/xeon e5/e5-1620 v4"
< intel‎ | xeon e5

m (Bot: moving all {{mpu}} to {{chip}})
 
Line 133: Line 133:
 
== Features ==  
 
== Features ==  
 
{{x86 features
 
{{x86 features
−
| em64t      = Yes
+
|real=No
−
| nx          = Yes
+
|protected=No
−
| txt        = Yes
+
|smm=No
−
| tsx        = Yes
+
|fpu=No
−
| vpro        = Yes
+
|x8616=No
−
| ht          = Yes
+
|x8632=No
−
| tbt1        =  
+
|x8664=No
−
| tbt2        = Yes
+
|nx=Yes
−
| tbmt3      = Yes
+
|mmx=Yes
−
| bpt        =  
+
|emmx=No
−
| vt-x        = Yes
+
|sse=Yes
−
| vt-d        = Yes
+
|sse2=Yes
−
| ept        = Yes
+
|sse3=Yes
−
| mmx        = Yes
+
|ssse3=Yes
−
| sse        = Yes
+
|sse41=No
−
| sse2        = Yes
+
|sse42=No
−
| sse3        = Yes
+
|sse4a=No
−
| ssse3      = Yes
+
|avx=Yes
−
| sse4.1      = Yes
+
|avx2=Yes
−
| sse4.2      = Yes
+
|avx512f=No
−
| aes        = Yes
+
|avx512cd=No
−
| pclmul      = Yes
+
|avx512er=No
−
| avx        = Yes
+
|avx512pf=No
−
| avx2        = Yes
+
|avx512bw=No
−
| bmi        = Yes
+
|avx512dq=No
−
| bmi1        = Yes
+
|avx512vl=No
−
| bmi2        = Yes
+
|avx512ifma=No
−
| f16c        = Yes
+
|avx512vbmi=No
−
| fma3        = Yes
+
|avx5124fmaps=No
−
| mpx        =  
+
|avx5124vnniw=No
−
| sgx        =  
+
|avx512vpopcntdq=No
−
| eist        = Yes
+
|abm=No
−
| secure key = Yes
+
|tbm=No
−
| os guard   = Yes
+
|bmi1=Yes
−
| intel at    =
+
|bmi2=Yes
−
| intel ipt   = Yes
+
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=No
 +
|sha=No
 +
|xop=No
 +
|adx=No
 +
|clmul=No
 +
|f16c=Yes
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=No
 +
|vtd=No
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|intqat=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|em64t=Yes
 +
|vt-x=Yes
 +
|vt-d=Yes
 +
|sse4_1=Yes
 +
|sse4_2=Yes
 +
|pclmul=Yes
 +
|bmi=Yes
 +
|secure key=Yes
 +
|os guard=Yes
 +
|intel ipt=Yes
 
}}
 
}}

Latest revision as of 00:04, 24 December 2017

Edit Values
Xeon E5-1620 v4
General Info
DesignerIntel
ManufacturerIntel
Model NumberE5-1620 v4
Part NumberCM8066002044103,
BX80660E51620V4
S-SpecSR2P6
QKF1 (QS)
MarketServer
IntroductionJune 20, 2016 (announced)
June 20, 2016 (launched)
Release Price$294.00
ShopAmazon
General Specs
FamilyXeon E5
SeriesE5-1000
LockedYes
Frequency3,500 MHz
Turbo FrequencyYes
Turbo Frequency3,800 MHz (1 core)
Bus typeDMI 2.0
Bus rate5 GT/s
Clock multiplier35
CPUID406F1
Microarchitecture
MicroarchitectureBroadwell
PlatformGrantley EP Workstation
ChipsetC610 Series
Core NameBroadwell EP
Core Family6
Core Model4F
Core SteppingR0
Process14 nm
Transistors3,200,000,000
TechnologyCMOS
Die246.24 mm²
Word Size64 bit
Cores4
Threads8
Max Memory1,536 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore1.82 V
VI/O1.2 V ± 3%
TDP140 W
Tcase0 °C – 69 °C
Tstorage-25 °C – 125 °C

The Xeon E5-1620 v4 is a 64-bit quad-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for 1S workstations. Operating at 3.5 GHz with a turbo boost frequency of 3.8 GHz for a single active core, this MPU has a TDP of 140 W and is manufactured on a 14 nm process (based on Broadwell).

Cache[edit]

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L1D$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
4x256 KiB 8-way set associative (per core, write-back)
L3$ 10 MiB
10,240 KiB
10,485,760 B
0.00977 GiB
4x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics[edit]

This microprocessor has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR4-2400
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 71.53 GiB/s
Bandwidth (single) 17.88 GiB/s
Bandwidth (dual) 35.76 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-1620_v4&oldid=71476"
Facts about "Xeon E5-1620 v4 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon E5-1620 v4 - Intel#io +
base frequency3,500 MHz (3.5 GHz, 3,500,000 kHz) +
bus rate5,000 MT/s (5 GT/s, 5,000,000 kT/s) +
bus typeDMI 2.0 +
chipsetC610 Series +
clock multiplier35 +
core count4 +
core family6 +
core model4F +
core nameBroadwell EP +
core steppingR0 +
core voltage1.82 V (18.2 dV, 182 cV, 1,820 mV) +
cpuid406F1 +
designerIntel +
die area246.24 mm² (0.382 in², 2.462 cm², 246,240,000 µm²) +
familyXeon E5 +
first announcedJune 20, 2016 +
first launchedJune 20, 2016 +
full page nameintel/xeon e5/e5-1620 v4 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureTrusted Execution Technology +, Transactional Synchronization Extensions +, Intel vPro Technology +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology + and Extended Page Tables +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
io voltage1.2 V (12 dV, 120 cV, 1,200 mV) +
io voltage tolerance3% +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description20-way set associative +
l3$ size10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) +
ldateJune 20, 2016 +
manufacturerIntel +
market segmentServer +
max case temperature342.15 K (69 °C, 156.2 °F, 615.87 °R) +
max cpu count1 +
max memory1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) +
max pcie lanes40 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureBroadwell +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature248.15 K (-25 °C, -13 °F, 446.67 °R) +
model numberE5-1620 v4 +
nameXeon E5-1620 v4 +
part numberCM8066002044103 + and BX80660E51620V4 +
platformGrantley EP Workstation +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 294.00 (€ 264.60, £ 238.14, ¥ 30,379.02) +
s-specSR2P6 +
s-spec (qs)QKF1 +
seriesE5-1000 +
smp max ways1 +
tdp140 W (140,000 mW, 0.188 hp, 0.14 kW) +
technologyCMOS +
thread count8 +
transistor count3,200,000,000 +
turbo frequency (1 core)3,800 MHz (3.8 GHz, 3,800,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +