From WikiChip
Difference between revisions of "intel/celeron/n3450"
< intel‎ | celeron

m (Bot: moving all {{mpu}} to {{chip}})
(Appolo lake chips support sse4.1 sse4.2)
 
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== Features ==  
 
== Features ==  
 
{{x86 features
 
{{x86 features
−
| em64t      = Yes
+
|real=No
−
| nx          = Yes
+
|protected=No
−
| txt        = Yes
+
|smm=No
−
| tsx        =  
+
|fpu=No
−
| vpro        =  
+
|x8616=No
−
| ht          =  
+
|x8632=No
−
| tbt1        =
+
|x8664=No
−
| tbt2        =  
+
|nx=Yes
−
| bpt        = Yes
+
|mmx=Yes
−
| vt-x        = Yes
+
|emmx=No
−
| vt-d        = Yes
+
|sse=Yes
−
| ept        = Yes
+
|sse2=Yes
−
| mmx        = Yes
+
|sse3=Yes
−
| sse        = Yes
+
|ssse3=Yes
−
| sse2        = Yes
+
|sse41=Yes
−
| sse3        = Yes
+
|sse42=Yes
−
| ssse3      = Yes
+
|sse4a=No
−
| sse4.1      = Yes
+
|sse_gfni=No
−
| sse4.2      = Yes
+
|avx=No
−
| aes        = Yes
+
|avx_gfni=No
−
| pclmul      = Yes
+
|avx2=No
−
| avx        =  
+
|avx512f=No
−
| avx2        =  
+
|avx512cd=No
−
| bmi        =  
+
|avx512er=No
−
| bmi1        =  
+
|avx512pf=No
−
| bmi2        =  
+
|avx512bw=No
−
| f16c        =  
+
|avx512dq=No
−
| fma3        =  
+
|avx512vl=No
−
| mpx        =  
+
|avx512ifma=No
−
| sgx        =  
+
|avx512vbmi=No
−
| eist        = Yes
+
|avx5124fmaps=No
−
| secure key  = Yes
+
|avx512vnni=No
−
| os guard    =  
+
|avx5124vnniw=No
−
| intel at    =  
+
|avx512vpopcntdq=No
 +
|avx512gfni=No
 +
|avx512vaes=No
 +
|avx512vbmi2=No
 +
|avx512bitalg=No
 +
|avx512vpclmulqdq=No
 +
|abm=No
 +
|tbm=No
 +
|bmi1=No
 +
|bmi2=No
 +
|fma3=No
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=No
 +
|sha=No
 +
|xop=No
 +
|adx=No
 +
|clmul=No
 +
|f16c=No
 +
|bfloat16=No
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|tvb=No
 +
|bpt=Yes
 +
|eist=Yes
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=Yes
 +
|ht=No
 +
|vpro=No
 +
|vtx=No
 +
|vtd=No
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|intqat=No
 +
|dlboost=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 +
|em64t=Yes
 +
|vt-x=Yes
 +
|vt-d=Yes
 +
|sse4_1=Yes
 +
|sse4_2=Yes
 +
|pclmul=Yes
 +
|secure key=Yes
 
}}
 
}}

Latest revision as of 22:15, 25 August 2019

Edit Values
Celeron N3450
General Info
DesignerIntel
ManufacturerIntel
Model NumberN3450
Part NumberFH8066802979803,
FH8066802979803
S-SpecSR2YA, SR2Z6
MarketMobile
IntroductionAugust 30, 2016 (announced)
August 30, 2016 (launched)
Release Price$107.00
ShopAmazon
General Specs
FamilyCeleron
SeriesN Series
LockedYes
Frequency1100 MHz
Turbo FrequencyYes
Turbo Frequency2200 MHz (1 core)
Clock multiplier11
Microarchitecture
MicroarchitectureGoldmont
Core NameApollo Lake
Core SteppingB0, B1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores4
Threads4
Max Memory8 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
SDP4 W
TDP6 W
Tjunction0 °C – 105 °C
Tstorage-25 °C – 125 °C

Celeron N3450 is a quad-core 64-bit x86 mobile microprocessor introduced by Intel in 2016. The processor is based on Goldmont microarchitecture and is manufactured on a 14 nm process. The chip operates at 1.1 GHz with burst frequency of 2.2 GHz and has a TDP of 6 W (SDP of 4 W). This MPU incorporates Intel's HD Graphics 500 GPU operating at 200 MHz with a burst frequency of 700 MHz.

Cache[edit]

Main article: Goldmont § Cache
Cache Info [Edit Values]
L1I$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core)
L1D$ 96 KiB
98,304 B
0.0938 MiB
4x24 KiB 6-way set associative (per core)
L2$ 2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
2x1 MiB 16-way set associative (per 2 cores)
L3$ 0 KiB
0 MiB
0 B
0 GiB
No L3$

Memory controller[edit]

Integrated Memory Controller
Type LPDDR3-1333, LPDDR3-1600, LPDDR3-2400, DDR3L-1333, DDR3L-1600, DDR3L-1867, LPDDR4-1600, LPDDR4-2133, LPDDR4-2400
Controllers 1
Channels 2
ECC Support No
Bandwidth (single) 19,200 MB/s
Bandwidth (dual) 38,400 MB/s
Max memory 8,192 MB

Graphics[edit]

Integrated Graphic Information
GPU HD Graphics 500
Device ID 0x5A85
Execution Units 12
Displays 3
Frequency 200 MHz
0.2 GHz
200,000 KHz
Max frequency 700 MHz
0.7 GHz
700,000 KHz
Max memory 8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
Output DisplayPort, Embedded DisplayPort, HDMI, DSI
DirectX 12
OpenGL 4.3
OpenCL 1.2
OpenGL ES 3.0
HDMI 1.4b
DP 1.2
eDP 1.3
Max HDMI Res 3840x2160 @30 Hz
Max DSI Res 2560x1600 @60 Hz
Max DP Res 4096x2160 @60 Hz
Max eDP Res 3840x2160 @60 Hz
Intel Quick Sync Video
Intel Clear Video
  • Video decode hardware acceleration including support for HEVC (H.265), H.264, MVC, VP8, VP9, MPEG2, VC-1, WMV9, JPEG/MJPEG.
  • Video encode hardware acceleration including support for HEVC (H.265), H.264, MVC, VP8, VP9, JPEG/MJPEG.

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision2.0
Max Lanes6
Configs4x1, 2x1 + 1x2 + 1x2
USB
Revision2.0, 3.0
Ports8
UART
SATA
Revision3.0
Ports3
GP I/OYes


  • 2x USB 2.0 ports
  • 6x USB 3.0 ports
    • 1x USB Dual Role
    • 1x Dedicated Port
    • 3x multiplexed with PCIe 2.0
    • 1x multiplexed with SATA 3.0

Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/celeron/n3450&oldid=93455"
Facts about "Celeron N3450 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Celeron N3450 - Intel#io +
base frequency1,100 MHz (1.1 GHz, 1,100,000 kHz) +
clock multiplier11 +
core count4 +
core nameApollo Lake +
core steppingB0 + and B1 +
designerIntel +
device id0x5A85 +
familyCeleron +
first announcedAugust 30, 2016 +
first launchedAugust 30, 2016 +
full page nameintel/celeron/n3450 +
has extended page tables supporttrue +
has featureintegrated gpu +, Advanced Encryption Standard Instruction Set Extension +, Burst Performance Technology +, Enhanced SpeedStep Technology +, Trusted Execution Technology + and Extended Page Tables +
has intel burst performance technologytrue +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
integrated gpuHD Graphics 500 +
integrated gpu base frequency200 MHz (0.2 GHz, 200,000 KHz) +
integrated gpu max frequency700 MHz (0.7 GHz, 700,000 KHz) +
integrated gpu max memory8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB) +
l1d$ description6-way set associative +
l1d$ size96 KiB (98,304 B, 0.0938 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description16-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l3$ descriptionNo L3$ +
l3$ size0 MiB (0 KiB, 0 B, 0 GiB) +
ldateAugust 30, 2016 +
manufacturerIntel +
market segmentMobile +
max cpu count1 +
max junction temperature378.15 K (105 °C, 221 °F, 680.67 °R) +
max memory8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) +
max pcie lanes6 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureGoldmont +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature248.15 K (-25 °C, -13 °F, 446.67 °R) +
model numberN3450 +
nameCeleron N3450 +
part numberFH8066802979803 +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 107.00 (€ 96.30, £ 86.67, ¥ 11,056.31) +
s-specSR2YA + and SR2Z6 +
sdp4 W (4,000 mW, 0.00536 hp, 0.004 kW) +
seriesN Series +
smp max ways1 +
tdp6 W (6,000 mW, 0.00805 hp, 0.006 kW) +
technologyCMOS +
thread count4 +
turbo frequency (1 core)2,200 MHz (2.2 GHz, 2,200,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +