Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "baikal/baikal-m"
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| thread count = 8 | | thread count = 8 | ||
| max cpus = | | max cpus = | ||
| − | | max memory = | + | | max memory = 128 GB |
| max memory addr = <!-- Max Addressable Memory --> | | max memory addr = <!-- Max Addressable Memory --> | ||
| Line 126: | Line 126: | ||
== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
| − | |type=DDR4- | + | |type=DDR4-2400 |
|ecc=Yes | |ecc=Yes | ||
| − | |max mem= | + | |max mem=128 GiB |
| − | |controllers= | + | |controllers=2 |
| − | |channels= | + | |channels=2 |
|max bandwidth=11.92 GiB/s | |max bandwidth=11.92 GiB/s | ||
|bandwidth schan=11.92 GiB/s | |bandwidth schan=11.92 GiB/s | ||
| Line 141: | Line 141: | ||
| designer = ARM Holdings | | designer = ARM Holdings | ||
| execution units = 8 | | execution units = 8 | ||
| − | | max displays = | + | | max displays = 2 |
| max memory = | | max memory = | ||
| − | | frequency = | + | | frequency = 850 MHz |
| output dsi = Yes | | output dsi = Yes | ||
| Line 159: | Line 159: | ||
{{expansions | {{expansions | ||
|pcie revision=3.0 | |pcie revision=3.0 | ||
| − | |pcie lanes= | + | |pcie lanes=16 |
| − | |pcie config=x4 | + | |pcie config=x4, x4, x8 |
| − | |usb revision=2.0 | + | |usb revision=2.0, 3.0 |
| − | |usb rate= | + | |usb rate= |
| − | |usb extra= | + | |usb extra= |
|uart=Yes | |uart=Yes | ||
| − | |uart ports= | + | |uart ports=3 |
|sata revision=3.1 | |sata revision=3.1 | ||
|sata ports=2 | |sata ports=2 | ||
|i2c=Yes | |i2c=Yes | ||
| − | |i2c ports= | + | |i2c ports=23t |
| − | |||
|jtag=Yes | |jtag=Yes | ||
|integrated lan=Yes | |integrated lan=Yes | ||
| Line 181: | Line 180: | ||
|1ge ports=2 | |1ge ports=2 | ||
|10ge=Yes | |10ge=Yes | ||
| − | |10ge ports= | + | |10ge ports=2 |
| − | |mii opts= | + | |mii opts= |
|rgmii=Yes | |rgmii=Yes | ||
|rgmii ports=2 | |rgmii ports=2 | ||
}} | }} | ||
Latest revision as of 08:26, 3 December 2019
| Edit Values | |
| Baikal-M | |
| General Info | |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Model Number | Baikal-M |
| Introduction | Jan 28, 2016 (announced) 2017 (launched) |
| General Specs | |
| Series | Baikal |
| Frequency | 2,000 MHz |
| Microarchitecture | |
| ISA | ARMv8 (ARM) |
| Microarchitecture | Cortex-A57 |
| Core Name | Cortex-A57 |
| Process | 28 nm |
| Cores | 8 |
| Threads | 8 |
| Max Memory | 128 GB |
Baikal-M is an octa-core 64-bit ARM system on a chip set to be introduced by Baikal Electronics in late 2017. This chip, which is fabricated on TSMC's 28 nm process, operates at 2 GHz and integrates an ARM Mali-T628 MP8 IGP.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Cache[edit]
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Graphics[edit]
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Integrated Graphics Information
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Expansions[edit]
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Expansion Options
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Networking[edit]
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Networking
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Facts about "Baikal-M - Baikal Electronics"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Baikal-M - Baikal Electronics#io + |
| base frequency | 2,000 MHz (2 GHz, 2,000,000 kHz) + |
| core count | 8 + |
| core name | Cortex-A57 + |
| designer | ARM Holdings + |
| first announced | January 28, 2016 + |
| first launched | 2017 + |
| full page name | baikal/baikal-m + |
| has ecc memory support | true + |
| instance of | microprocessor + |
| integrated gpu | Mali-T628 + |
| integrated gpu designer | ARM Holdings + |
| integrated gpu execution units | 8 + |
| isa | ARMv8 + |
| isa family | ARM + |
| l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
| ldate | 3000 + |
| manufacturer | TSMC + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 1 + |
| max pcie lanes | 4 + |
| microarchitecture | Cortex-A57 + |
| model number | Baikal-M + |
| name | Baikal-M + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + |
| series | Baikal + |
| supported memory type | DDR4-1600 + |
| thread count | 8 + |