From WikiChip
Difference between revisions of "intel/celeron/g4950"
< intel‎ | celeron

(Created page with "{{intel title|Celeron G4950}} {{mpu}}")
 
Line 1: Line 1:
 
{{intel title|Celeron G4950}}
 
{{intel title|Celeron G4950}}
−
{{mpu}}
+
{{mpu
 +
|future=Yes
 +
|name=Celeron G4950
 +
|image=coffee lake s (front).png
 +
|designer=Intel
 +
|manufacturer=Intel
 +
|model number=G4950
 +
|family=Celeron
 +
|series=4000
 +
|locked=Yes
 +
|bus type=DMI 3.0
 +
|bus links=4
 +
|bus rate=8 GT/s
 +
|isa=x86-64
 +
|isa family=x86
 +
|microarch=Coffee Lake
 +
|core name=Coffee Lake S
 +
|process=14 nm
 +
|technology=CMOS
 +
|die area=149 mm²
 +
|word size=64 bit
 +
|core count=2
 +
|thread count=2
 +
|max cpus=1
 +
|max memory=64 GiB
 +
|package module 1={{packages/intel/lga-1151}}
 +
}}

Revision as of 09:41, 24 November 2017

Template:mpu

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/celeron/g4950&oldid=67564"