From WikiChip
Difference between revisions of "intel/xeon gold/6146"
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{{benchmarks main | {{benchmarks main | ||
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− | {{benchmark entry}} | + | {{benchmark entry |
+ | |type=spec | ||
+ | |test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00414.html | ||
+ | |test_timestamp=2017-10-22 23:24:41-0400 | ||
+ | |chip_count=2 | ||
+ | |core_count=24 | ||
+ | |copies_count=48 | ||
+ | |vendor=Cisco Systems | ||
+ | |system=Cisco UCS B200 M5 (Intel Xeon Gold 6146, 3.20GHz) | ||
+ | |SPECrate2017_fp_base=168 | ||
+ | |SPECrate2017_fp_peak=171 | ||
+ | }} | ||
}} | }} | ||
[[Category:microprocessor models by intel based on skylake extreme core count die]] | [[Category:microprocessor models by intel based on skylake extreme core count die]] |
Revision as of 02:14, 24 November 2017
Template:mpu Xeon Gold 6146 is a 64-bit dodeca-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6146, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 3.2 GHz with a TDP of 165 W and a turbo boost frequency of up to 4.2 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
Cache
- Main article: Skylake § Cache
The Xeon Gold 6146 features a considerably larger non-default 24.75 MiB of L3, a size that would normally be found on an 18-core part.
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Frequencies
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||
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1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | ||
Normal | 3,200 MHz | 4,200 MHz | 4,200 MHz | 4,100 MHz | 4,100 MHz | 4,000 MHz | 4,000 MHz | 4,000 MHz | 4,000 MHz | 3,900 MHz | 3,900 MHz | 3,900 MHz | 3,900 MHz |
AVX2 | 2,600 MHz | 3,600 MHz | 3,600 MHz | 3,400 MHz | 3,400 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz |
AVX512 | 2,100 MHz | 3,500 MHz | 3,500 MHz | 3,300 MHz | 3,300 MHz | 3,100 MHz | 3,100 MHz | 3,100 MHz | 3,100 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz |
Benchmarks
Facts about "Xeon Gold 6146 - Intel"