Semiconductor & Computer Engineering
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Difference between revisions of "qualcomm/centriq/2452"
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|bandwidth qchan=79.47 GiB/s | |bandwidth qchan=79.47 GiB/s | ||
|bandwidth hchan=119.21 GiB/s | |bandwidth hchan=119.21 GiB/s | ||
| + | }} | ||
| + | |||
| + | == Expansions == | ||
| + | {{expansions main | ||
| + | | | ||
| + | {{expansions entry | ||
| + | |type=PCIe | ||
| + | |pcie revision=3.0 | ||
| + | |pcie lanes=32 | ||
| + | |pcie config=x16 | ||
| + | |pcie config 2=x8 | ||
| + | |pcie config 3=x4 | ||
| + | }} | ||
| + | {{expansions entry | ||
| + | |type=SATA | ||
| + | |sata revision=3.0 | ||
| + | |sata ports=8 | ||
| + | }} | ||
}} | }} | ||
Revision as of 03:00, 9 November 2017
Template:mpu Centriq 2452 is a 64-bit 46-core ARM high-performance server microprocessor designed by Qualcomm and introduced in late 2017. This processor, which is based on the Falkor microarchitecture, is fabricated on Samsung's 10LPE process. The 2452 has a based frequency of 2.2 GHz with a TDP of 120 W and a turbo frequency of 2.6 GHz. This chip supports up to 768 GiB of hexa-channel DDR4-2666 memory.
Cache
- Main article: Falkor § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options |
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Facts about "Centriq 2452 - Qualcomm"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Centriq 2452 - Qualcomm#pcie + |
| has ecc memory support | true + |
| l1$ size | 4,416 KiB (4,521,984 B, 4.313 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 1,472 KiB (1,507,328 B, 1.438 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 2,944 KiB (3,014,656 B, 2.875 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 11.5 MiB (11,776 KiB, 12,058,624 B, 0.0112 GiB) + |
| l3$ description | 20-way set associative + |
| l3$ size | 57.5 MiB (58,880 KiB, 60,293,120 B, 0.0562 GiB) + |
| max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
| max memory channels | 6 + |
| max sata ports | 8 + |
| supported memory type | DDR4-2666 + |