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Difference between revisions of "zettascaler"

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=== ZettaScaler-1.x ===
 
=== ZettaScaler-1.x ===
'''ZettaScaler-1''' ('''ZS-1''') is based on the {{pezy|PEZY-SC}}
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'''ZettaScaler-1.x''' ('''ZS-1.x''') is based on the {{pezy|PEZY-SC}}. Each node (brick) was constructed using two {{intel|Xeon E5}} connected using [[Intel]]'s {{intel|QPI}} along with 4 set of dual PEZY-SC chips in PCIe card slots using InfiniBand FDR HCA. The use of the general-purpose Intel chips was to reduce cost and speedup development cycle.
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With the introduction of the ZS-1.6, PEZY redesigned the package of the PEZY-SC. The new chip, {{pezy|PEZY-SCnp}} (NP for New Package), addressed a number of issues relating to signal quality (DRAM, and PCIe frequency failure).
  
 
=== ZettaScaler-2.x ===
 
=== ZettaScaler-2.x ===

Revision as of 02:13, 2 November 2017

ZettaScaler is a series of Japanese supercomputers using processors designed by PEZY and liquid cooling systems designed by ExaScaler.

Overview

ZettaScaler supercomputers are constructed using dense server aggregates called 'Bricks'. The system is cooled using enclosures containing a number of bricks. The cooling system is designed by ExaScaler and makes use of 3M's Fluorinert Electronic liquid which is an electrically insulating fluorocarbon-based inert liquid.

ZettaScaler-1.x

ZettaScaler-1.x (ZS-1.x) is based on the PEZY-SC. Each node (brick) was constructed using two Xeon E5 connected using Intel's QPI along with 4 set of dual PEZY-SC chips in PCIe card slots using InfiniBand FDR HCA. The use of the general-purpose Intel chips was to reduce cost and speedup development cycle.

With the introduction of the ZS-1.6, PEZY redesigned the package of the PEZY-SC. The new chip, PEZY-SCnp (NP for New Package), addressed a number of issues relating to signal quality (DRAM, and PCIe frequency failure).

ZettaScaler-2.x

With the introduction of the ZettaScaler-2.x, PEZY has redesigned the Brick. PEZY moved to an advanced 3D packaging technology using ThruChip Interface (TCI) to interconnect the DRAM to the processor which uses wireless near-field inductive coupling instead of the traditional TSV.

References