From WikiChip
Difference between revisions of "amd/ryzen 7/2700u"
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+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=No | ||
+ | |avx512dq=No | ||
+ | |avx512vl=No | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx5124vnniw=No | ||
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+ | |kpt=No | ||
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|rvi=No | |rvi=No | ||
|smt=Yes | |smt=Yes | ||
|sensemi=Yes | |sensemi=Yes | ||
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Revision as of 23:57, 26 October 2017
Template:mpu Ryzen 7 2700U is a 64-bit quad-core high-end performance x86 mobile microprocessor introduced by AMD in late 2017. This processor is based on AMD's Zen microarchitecture and is fabricated on a 14 nm process. The 2700U operates at a base frequency of 2.2 GHz with a TDP of 15 W and a Boost frequency of 3.8 GHz. This MPU supports up to ? GiB of dual-channel DDR4-2400 memory and incorporates Radeon Vega 10 Graphics operating at up to 1.1 GHz.
This model supports a configurable TDP-down of 12 W and TDP-up of 25 W.
Cache
- Main article: Zen § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options |
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Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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Die Shot
- Further information: Zen § Die Shot
- 14 nm process
- 4,950,000,000 transistors
- 209.78 mm² die size
Facts about "Ryzen 7 2700U - AMD"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Ryzen 7 2700U - AMD#pcie + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has amd amd-v technology | true + |
has amd amd-vi technology | true + |
has amd extended frequency range | true + |
has amd sensemi technology | true + |
has ecc memory support | false + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology + and Extended Frequency Range + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
max memory bandwidth | 35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) + |
max memory channels | 2 + |
supported memory type | DDR4-2400 + |