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+ | == Neural Network Processing Unit (NPU) == | ||
+ | [[File:kirin 970 npu.png|right|350px]] | ||
+ | The Kirin 970 incorporates a new Neural Network Processing Unit (NPU) designed specifically to be used as an AI accelerator. According to CEO Mr. Richard Yu who introduced the Kirin 970 at 2017 IFA, the NPU uses up the die area of roughly half of the CPU while consuming 50% less power and performing around 25 times faster than a traditional CPU for tasks such as photo recognition. The exact architectural detials of the NPU have been withheld. The NPU is said to deliver 1.92 [[TFLOP]]s (HP 16-bit). |
Revision as of 13:44, 7 September 2017
Template:mpu Kirin 970 is a 64-bit octa-core high-performance mobile ARM LTE SoC introduced by HiSilicon in mid-2017 at the 2017 IFA. This chip, which is fabricated on a 10 nm process, features four Cortex-A73 big cores operating at up to 2.4 GHz along with four Cortex-A53 little cores operating at up to 1.8 GHz. The 970 incorporates ARM's Mali G72 (12 core) IGP operating at ? MHz and supports up to 6 GiB of dual-channel LPDDR4-1866 memory.
Introduced at the 2017 IFA, the overall core organization is identical to the Kirin 960 which was introduced the previous year, but features 20% power efficiency and 40% smaller die area due to the process shrink. The 970 ballooned to over 37.5% more transistors from 4 billion in the 960 to 5.5 billion. The 970 adds many enhancements, including a more powerful Mali G72 GPU and incorporates a new Neural Network Processing Unit (NPU) designed for AI acceleration. The 970 has two improved ISPs and a more powerful LTE modem supporting up to User Equipment (UE) category 18 capable of reaching a maximum downlink of 1.2 Gbps (4x4 MIMO, 256 QAM, 3CC CA).
Cache
- Main articles: Cortex-A53 § Cache and Cortex-A73 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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This section requires expansion; you can help adding the missing info. |
Memory controller
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Integrated Memory Controller
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Graphics
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Integrated Graphics Information
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Neural Network Processing Unit (NPU)
The Kirin 970 incorporates a new Neural Network Processing Unit (NPU) designed specifically to be used as an AI accelerator. According to CEO Mr. Richard Yu who introduced the Kirin 970 at 2017 IFA, the NPU uses up the die area of roughly half of the CPU while consuming 50% less power and performing around 25 times faster than a traditional CPU for tasks such as photo recognition. The exact architectural detials of the NPU have been withheld. The NPU is said to deliver 1.92 TFLOPs (HP 16-bit).
has ecc memory support | false + |
integrated gpu | Mali-G72 + |
integrated gpu base frequency | 850 MHz (0.85 GHz, 850,000 KHz) + |
integrated gpu designer | ARM Holdings + |
integrated gpu execution units | 12 + |
max memory bandwidth | 27.82 GiB/s (28,487.68 MiB/s, 29.871 GB/s, 29,871.498 MB/s, 0.0272 TiB/s, 0.0299 TB/s) + |
max memory channels | 2 + |
supported memory type | LPDDR4-1866 + |