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Introduced at the 2017 IFA, the overall core organization is identical to the {{\\|960|Kirin 960}} which was introduced the previous year, but features 20% power efficiency and 40% smaller [[die area]] due to the [[process shrink]]. The 970 adds many enhancements, including a more powerful {{armh|Mali G72}} GPU and incorporates a new Neural Network Processing Unit (NPU) designed for [[AI]] acceleration. The 970 has two improved [[image signal processor|ISP]]s and a more powerful LTE modem supporting up to [[User Equipment]] (UE) category 18 capable of reaching a maximum downlink of 1.2 Gbps (4x4 MIMO, 256 QAM, 3CC CA). | Introduced at the 2017 IFA, the overall core organization is identical to the {{\\|960|Kirin 960}} which was introduced the previous year, but features 20% power efficiency and 40% smaller [[die area]] due to the [[process shrink]]. The 970 adds many enhancements, including a more powerful {{armh|Mali G72}} GPU and incorporates a new Neural Network Processing Unit (NPU) designed for [[AI]] acceleration. The 970 has two improved [[image signal processor|ISP]]s and a more powerful LTE modem supporting up to [[User Equipment]] (UE) category 18 capable of reaching a maximum downlink of 1.2 Gbps (4x4 MIMO, 256 QAM, 3CC CA). | ||
+ | |||
+ | == Cache == | ||
+ | {{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a73#Memory_Hierarchy|l1=Cortex-A53 § Cache|l2=Cortex-A73 § Cache}} | ||
+ | {{cache size}} |
Revision as of 09:02, 7 September 2017
Template:mpu Kirin 970 is a 64-bit octa-core high-performance mobile ARM LTE SoC introduced by HiSilicon in mid-2017 at the 2017 IFA. This chip, which is fabricated on a 10 nm process, features four Cortex-A73 big cores operating at up to 2.4 GHz along with four Cortex-A53 little cores operating at up to 1.8 GHz. The 970 incorporates ARM's Mali G72 (12 core) IGP operating at ? MHz and supports up to 6 GiB of dual-channel LPDDR4-1866 memory.
Introduced at the 2017 IFA, the overall core organization is identical to the Kirin 960 which was introduced the previous year, but features 20% power efficiency and 40% smaller die area due to the process shrink. The 970 adds many enhancements, including a more powerful Mali G72 GPU and incorporates a new Neural Network Processing Unit (NPU) designed for AI acceleration. The 970 has two improved ISPs and a more powerful LTE modem supporting up to User Equipment (UE) category 18 capable of reaching a maximum downlink of 1.2 Gbps (4x4 MIMO, 256 QAM, 3CC CA).
Cache
- Main articles: Cortex-A53 § Cache and Cortex-A73 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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base frequency | 1,800 MHz (1.8 GHz, 1,800,000 kHz) + and 2,360 MHz (2.36 GHz, 2,360,000 kHz) + |
core count | 8 + |
core name | Cortex-A53 + and Cortex-A73 + |
designer | HiSilicon + and ARM Holdings + |
die area | 96.72 mm² (0.15 in², 0.967 cm², 96,720,000 µm²) + |
die length | 9.75 mm (0.975 cm, 0.384 in, 9,750 µm) + |
die width | 9.92 mm (0.992 cm, 0.391 in, 9,920 µm) + |
family | Kirin + |
first announced | September 1, 2017 + |
first launched | September 1, 2017 + |
full page name | hisilicon/kirin/970 + |
has ecc memory support | false + |
instance of | microprocessor + |
integrated gpu | Mali-G72 + |
integrated gpu base frequency | 746 MHz (0.746 GHz, 746,000 KHz) + |
integrated gpu designer | ARM Holdings + |
integrated gpu execution units | 12 + |
isa | ARMv8 + |
isa family | ARM + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + and 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + and 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + and 128 KiB (131,072 B, 0.125 MiB) + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + and 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
ldate | September 1, 2017 + |
main image | + |
manufacturer | TSMC + |
market segment | Mobile + |
max cpu count | 1 + |
max memory | 8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) + |
max memory bandwidth | 27.82 GiB/s (28,487.68 MiB/s, 29.871 GB/s, 29,871.498 MB/s, 0.0272 TiB/s, 0.0299 TB/s) + |
max memory channels | 4 + |
microarchitecture | Cortex-A53 + and Cortex-A73 + |
model number | 970 + |
name | Kirin 970 + |
part number | Hi3670 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |
series | 900 + |
smp max ways | 1 + |
supported memory type | LPDDR4X-3732 + |
technology | CMOS + |
thread count | 8 + |
transistor count | 5,500,000,000 + |
used by | Huawei Mate 10 +, Huawei Mate 10 Pro +, Huawei Mate 10 Porsche Design +, Huawei Mate RS Porsche Design +, Huawei P20 +, Huawei P20 Pro +, Huawei Nova 3 +, Huawei Nova 4 +, Honor V10 (Honor View 10) +, Honor 10 +, Honor Play 2 +, Honor Note 10 +, HiKey 970 +, Honor 8 Pro + and Honor Play + |
word size | 64 bit (8 octets, 16 nibbles) + |