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Difference between revisions of "hisilicon/k3/k3v1"
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|manufacturer=TSMC | |manufacturer=TSMC | ||
|model number=K3V1 | |model number=K3V1 |
Revision as of 00:22, 6 September 2017
Template:mpu K3V1 is a 32-bit performance ARM microprocessor introduced by HiSilicon in 2008. This chip incorporates a single ARM9 core with Jazelle support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory.
Contents
Cache
- Main article: ARM9 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
- 4x high-speed UART interfaces
- 2x SPI
- 2x I2C
- USB 2.0 On-The-Go (HS OTG) PHY
- USB 1.1
- 2x MMC/SD/SDIO interface
- 14x GPIOs
- 8 Timers
Graphics
The K3V1 integrated graphics engine, although the exact specs are not available. This GPU is most likely a licensed Vivante core.
- Support QVGA, WQVGA, VGA display resolutions
- Hardware-acceleration video
- 200 KiB Frame Buffer
Camera
- Support 30 million pixel camera, up to 30fps
- Supports up to 8 megapixel CMOS Sensor image input
Audio
- Built-in high-performance audio CODEC
- Sampling frequency support 44.1kHz and 48kHz
- support for sound playback and recording
- High quality stereo playback DAC and 1 channel Voice DAC, 2 channels
- ADC, CODEC support any audio mixing, independent of the amplifier Output gain control
Block Diagram
Documents
Facts about "K3V1 - HiSilicon"
has ecc memory support | false + |
l1$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1d$ description | 4-way set associative + |
l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
max memory channels | 1 + |
supported memory type | DDR + |