Semiconductor & Computer Engineering
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Difference between revisions of "hisilicon/k3/k3v1"
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|package module 1={{packages/hisilicon/tfbga-460}} | |package module 1={{packages/hisilicon/tfbga-460}} | ||
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Revision as of 00:52, 6 September 2017
Template:mpu K3V1 is a 32-bit performance ARM microprocessor introduced by HiSilicon in 2008. This chip incorporates a single ARM9 core with Jazelle support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory.
Cache
- Main article: ARM9 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Documents
Facts about "K3V1 - HiSilicon"
| has ecc memory support | false + |
| l1$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| max memory channels | 1 + |
| supported memory type | DDR + |