From WikiChip
Difference between revisions of "hisilicon/k3/k3v1"
< hisilicon‎ | k3

Line 26: Line 26:
 
}}
 
}}
 
'''K3V1''' is a {{arch|32}} performance [[ARM]] microprocessor introduced by [[HiSilicon]] in [[2008]]. This chip incorporates a [[single core|single]] {{armh|ARM9}} core with {{arm|Jazelle}} support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory.
 
'''K3V1''' is a {{arch|32}} performance [[ARM]] microprocessor introduced by [[HiSilicon]] in [[2008]]. This chip incorporates a [[single core|single]] {{armh|ARM9}} core with {{arm|Jazelle}} support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory.
 +
 +
== Cache ==
 +
{{main|arm holdings/microarchitectures/arm9#Memory_Hierarchy|l1=ARM9 § Cache}}
 +
{{cache size
 +
|l1 cache = 32 KiB
 +
|l1i cache=16 KiB
 +
|l1i break=1x16 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=16 KiB
 +
|l1d break=1x16 KiB
 +
|l1d desc=4-way set associative
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR
 +
|controllers=1
 +
|channels=1
 +
|width=16 bit
 +
|width 2=32 bit
 +
}}
 +
 +
 +
 +
== Documents ==
 +
* [[:File:k3v1 prod brief.pdf|K3V1 Product Brief]]

Revision as of 00:52, 6 September 2017

Template:mpu K3V1 is a 32-bit performance ARM microprocessor introduced by HiSilicon in 2008. This chip incorporates a single ARM9 core with Jazelle support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory.

Cache

Main article: ARM9 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$32 KiB
32,768 B
0.0313 MiB
L1I$16 KiB
16,384 B
0.0156 MiB
1x16 KiB4-way set associative 
L1D$16 KiB
16,384 B
0.0156 MiB
1x16 KiB4-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR
Controllers1
Channels1
Width16 bit, 32 bit


Documents

Retrieved from "https://en.wikichip.org/w/index.php?title=hisilicon/k3/k3v1&oldid=63532"
Facts about "K3V1 - HiSilicon"
RDF feed
has ecc memory supportfalse +
l1$ size32 KiB (32,768 B, 0.0313 MiB) +
l1d$ description4-way set associative +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description4-way set associative +
l1i$ size16 KiB (16,384 B, 0.0156 MiB) +
max memory channels1 +
supported memory typeDDR +