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Difference between revisions of "hisilicon/k3/k3v1"
< hisilicon‎ | k3

(Created page with "{{hisilicon title|K3V1}} {{mpu}} '''K3V1''' is a {{arch|32}} performance ARM microprocessor introduced by HiSilicon in 2008. This chip incorporates a single core...")
 
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{{hisilicon title|K3V1}}
 
{{hisilicon title|K3V1}}
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{{mpu}}
+
{{mpu
 +
|name=K3V1
 +
|no image=Yes
 +
|designer=HiSilicon
 +
|manufacturer=TSMC
 +
|model number=K3V1
 +
|part number=Hi3611
 +
|market=Mobile
 +
|first announced=June, 2008
 +
|first launched=June, 2008
 +
|family=K3
 +
|frequency=460
 +
|isa=ARMv5
 +
|isa family=ARM
 +
|microarch=ARM9
 +
|core name=ARM926EJ-S
 +
|process=0.18 µm
 +
|transistors=200,000,000
 +
|technology=CMOS
 +
|word size=32 bit
 +
|core count=1
 +
|thread count=1
 +
|max cpus=1
 +
|package module 1={{packages/hisilicon/tfbga-460}}
 +
}}
 
'''K3V1''' is a {{arch|32}} performance [[ARM]] microprocessor introduced by [[HiSilicon]] in [[2008]]. This chip incorporates a [[single core|single]] {{armh|ARM9}} core with {{arm|Jazelle}} support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory.
 
'''K3V1''' is a {{arch|32}} performance [[ARM]] microprocessor introduced by [[HiSilicon]] in [[2008]]. This chip incorporates a [[single core|single]] {{armh|ARM9}} core with {{arm|Jazelle}} support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory.

Revision as of 22:57, 5 September 2017

Template:mpu K3V1 is a 32-bit performance ARM microprocessor introduced by HiSilicon in 2008. This chip incorporates a single ARM9 core with Jazelle support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory.

Retrieved from "https://en.wikichip.org/w/index.php?title=hisilicon/k3/k3v1&oldid=63517"
Facts about "K3V1 - HiSilicon"
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K3V1 - HiSilicon#package +
base frequency460 MHz (0.46 GHz, 460,000 kHz) +
core count1 +
core nameARM926EJ-S +
designerHiSilicon + and ARM Holdings +
familyK3 +
first announcedJune 2008 +
first launchedJune 2008 +
full page namehisilicon/k3/k3v1 +
has ecc memory supportfalse +
instance ofmicroprocessor +
io voltage1.8 V (18 dV, 180 cV, 1,800 mV) + and 2.5 V (25 dV, 250 cV, 2,500 mV) +
isaARMv5 +
isa familyARM +
l1$ size32 KiB (32,768 B, 0.0313 MiB) +
l1d$ description4-way set associative +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description4-way set associative +
l1i$ size16 KiB (16,384 B, 0.0156 MiB) +
ldateJune 2008 +
manufacturerTSMC +
market segmentMobile +
max cpu count1 +
max memory channels1 +
microarchitectureARM9 +
model numberK3V1 +
nameK3V1 +
packageTFBGA-460 +
part numberHi3611 +
process180 nm (0.18 μm, 1.8e-4 mm) +
smp max ways1 +
supported memory typeDDR +
technologyCMOS +
thread count1 +
transistor count200,000,000 +
word size32 bit (4 octets, 8 nibbles) +