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Difference between revisions of "intel/core i7/i7-8550u"
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|manufacturer=Intel | |manufacturer=Intel | ||
|model number=i7-8550U | |model number=i7-8550U | ||
+ | |part number=FJ8067703281816 | ||
+ | |s-spec=SR3LC | ||
|market=Mobile | |market=Mobile | ||
+ | |first announced=August 21, 2017 | ||
+ | |first launched=August 21, 2017 | ||
|release price=$409.00 | |release price=$409.00 | ||
|family=Core i7 | |family=Core i7 | ||
− | |series=i7- | + | |series=i7-8000 |
|locked=Yes | |locked=Yes | ||
|frequency=1,800 MHz | |frequency=1,800 MHz | ||
Line 16: | Line 20: | ||
|bus type=OPI | |bus type=OPI | ||
|bus rate=4 GT/s | |bus rate=4 GT/s | ||
+ | |clock multiplier=18 | ||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
− | |microarch= | + | |microarch=Kaby Lake |
− | |platform= | + | |platform=Kaby Lake |
− | |core name= | + | |core name=Kaby Lake R |
+ | |core family=6 | ||
+ | |core model=142 | ||
+ | |core stepping=Y0 | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
Line 35: | Line 43: | ||
|tstorage min=-25 °C | |tstorage min=-25 °C | ||
|tstorage max=125 °C | |tstorage max=125 °C | ||
+ | |package module 1={{packages/intel/fcbga-1356}} | ||
|turbo frequency=Yes | |turbo frequency=Yes | ||
}} | }} |
Revision as of 04:10, 21 August 2017
Template:mpu Core i7-8550U is a 64-bit quad-core performance x86 mobile microprocessor set to be introduced by Intel in late 2017. This processor, which is based on the Coffee Lake microarchitecture, is manufactured on Intel's 3rd generation enhanced 14nm++ process. The i7-8550U operates at 1.8 GHz with a TDP of 15 W and with a Turbo Boost frequency of 4.0 GHz for a single active core. This MPU supports up to 32 GiB of dual-channel non-ECC DDR4-2133 memory.
Cache
- Main article: Coffee Lake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Graphics
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This section is empty; you can help add the missing info by editing this page. |
Features
[Edit/Modify Supported Features]
Facts about "Core i7-8550U - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i7-8550U - Intel#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology + and My WiFi Technology + |
has intel enhanced speedstep technology | true + |
has intel flex memory access support | true + |
has intel my wifi technology support | true + |
has intel secure key technology | true + |
has intel smart response technology support | true + |
has intel speed shift technology | true + |
has intel supervisor mode execution protection | true + |
has intel turbo boost technology 2 0 | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 12 + |
supported memory type | LPDDR3-1866 +, DDR3L-1600 + and DDR4-2133 + |
x86/has memory protection extensions | true + |
x86/has software guard extensions | true + |