Semiconductor & Computer Engineering
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Difference between revisions of "intel/atom/c3858"
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== Memory controller == | == Memory controller == | ||
| − | {{memory controller}} | + | {{memory controller |
| + | |type=DDR3L-1600 | ||
| + | |type 2=DDR4-2400 | ||
| + | |ecc=Yes | ||
| + | |max mem=256 GiB | ||
| + | |controllers=1 | ||
| + | |channels=2 | ||
| + | |max bandwidth=35.76 GiB/s | ||
| + | |bandwidth schan=17.88 GiB/s | ||
| + | |bandwidth dchan=35.76 GiB/s | ||
| + | }} | ||
Revision as of 23:42, 15 August 2017
Template:mpu Atom C3858 is a 64-bit dodeca-core ultra-low power x86 microserver system on a chip introduced by Intel in 2017. The C3858, which is manufactured on a 14 nm process, is based on the Goldmont microarchitecture. This chip operates at 2 GHz with a TDP of 25 W. The C3858 supports up to a dual-channel of 256 GiB of DDR4-2400 ECC memory.
Cache
- Main article: Goldmont § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Facts about "Atom C3858 - Intel"
| has ecc memory support | false + |
| l1$ size | 672 KiB (688,128 B, 0.656 MiB) + |
| l1d$ description | 6-way set associative + |
| l1d$ size | 288 KiB (294,912 B, 0.281 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) + |