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Difference between revisions of "intel/atom/c3958"
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'''Atom C3958''' is a {{arch|64}} [[hexadeca-core]] ultra-low power [[x86]] microserver [[system on a chip]] introduced by [[Intel]] in 2017. The C3958, which is manufactured on a [[14 nm process]], is based on the {{intel|Goldmont|l=arch}} microarchitecture. This chip operates at 2 GHz with a [[TDP]] of 31 W. The C3958 supports up to a dual-channel of 256 GiB of DDR4-2400 [[ECC]] memory. | '''Atom C3958''' is a {{arch|64}} [[hexadeca-core]] ultra-low power [[x86]] microserver [[system on a chip]] introduced by [[Intel]] in 2017. The C3958, which is manufactured on a [[14 nm process]], is based on the {{intel|Goldmont|l=arch}} microarchitecture. This chip operates at 2 GHz with a [[TDP]] of 31 W. The C3958 supports up to a dual-channel of 256 GiB of DDR4-2400 [[ECC]] memory. | ||
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| + | == Cache == | ||
| + | {{main|intel/microarchitectures/goldmont#Memory_Hierarchy|l1=Goldmont § Cache}} | ||
| + | {{cache size}} | ||
Revision as of 20:55, 15 August 2017
Template:mpu Atom C3958 is a 64-bit hexadeca-core ultra-low power x86 microserver system on a chip introduced by Intel in 2017. The C3958, which is manufactured on a 14 nm process, is based on the Goldmont microarchitecture. This chip operates at 2 GHz with a TDP of 31 W. The C3958 supports up to a dual-channel of 256 GiB of DDR4-2400 ECC memory.
Cache
- Main article: Goldmont § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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