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Difference between revisions of "renesas/r-car/h3 (sip)"
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|die width=8.61 mm | |die width=8.61 mm | ||
|word size=64 bit | |word size=64 bit | ||
− | |core count= | + | |core count=9 |
− | |thread count= | + | |thread count=9 |
|max cpus=1 | |max cpus=1 | ||
|v core=0.8 V | |v core=0.8 V | ||
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|package module 1={{packages/renesas/fcbga-1255}} | |package module 1={{packages/renesas/fcbga-1255}} | ||
}} | }} | ||
− | '''R-Car H3''' is a {{arch|64}} [[ | + | '''R-Car H3''' is a {{arch|64}} [[nona-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The H3 incorporates four {{armh|Cortex-A57}} cores, four {{armh|Cortex-A53}} cores, and a dual-core lock-step {{armh|Cortex-R7}} for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory. This chip incorporates the [[imagination technologies|Imagination]]'s {{imgtec|PowerVR GX6650}} [[GPU]]. |
This model is an [[SiP]] variant of the {{\\|H3}} which include the DDR memory on-package. | This model is an [[SiP]] variant of the {{\\|H3}} which include the DDR memory on-package. | ||
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{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a57#Memory_Hierarchy|l1=Cortex-A53 § Cache|l2=Cortex-A57 § Cache}} | {{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a57#Memory_Hierarchy|l1=Cortex-A53 § Cache|l2=Cortex-A57 § Cache}} | ||
{{cache size | {{cache size | ||
− | |l1 cache= | + | |l1 cache=640 KiB |
− | |l1i cache= | + | |l1i cache=352 KiB |
− | |l1i break=4x48+ | + | |l1i break=4x48+5x32 KiB |
− | |l1d cache= | + | |l1d cache=288 KiB |
− | |l1d break= | + | |l1d break=9x32 KiB |
|l2 cache=2.5 MiB | |l2 cache=2.5 MiB | ||
}} | }} | ||
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== Block Diagram == | == Block Diagram == | ||
:: [[File:r-car h3 block.png|750px]] | :: [[File:r-car h3 block.png|750px]] | ||
+ | |||
+ | == Die Shot == | ||
+ | * [[16 nm process]], CMOS FinFET | ||
+ | * 12.94 mm × 8.61 mm | ||
+ | * 111.36 mm² die size | ||
+ | |||
+ | |||
+ | :: [[File:r-car h3 die shot.png|650px]] | ||
+ | |||
+ | == References == | ||
+ | * Takahashi, Chikafumi, et al. "4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10− 7 random hardware failures per hour reliability." Solid-State Circuits Conference (ISSCC), 2016 IEEE International. IEEE, 2016. |
Revision as of 06:09, 23 July 2017
Template:mpu R-Car H3 is a 64-bit nona-core ARM SoC designed by Renesas for the automotive industry and introduced in 2016. The H3 incorporates four Cortex-A57 cores, four Cortex-A53 cores, and a dual-core lock-step Cortex-R7 for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory. This chip incorporates the Imagination's PowerVR GX6650 GPU.
This model is an SiP variant of the H3 which include the DDR memory on-package.
Samples for the H3 were available starting December 2015 with Renesas expecting mass production to begin in March 2018 and reach a volume of 100,000 units per month in March 2019.
Contents
Cache
- Main articles: Cortex-A53 § Cache and Cortex-A57 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
- PCI Express2.0 (1 lane) x 2 ch
- USB 3.0 Host interface (DRD) × 1 ports (wPHY)
- USB 2.0 Host/Function/OTG interface × 2 ports (wPHY)
- SD Host interface × 4 ch (SDR104)
- Multimedia card interface × 2 ch
- Serial ATA interface × 1 ch
- Media local bus (MLB) Interface × 1 ch (3 pin interface)
- Controller Area Network (CAN-FD support) Interface × 2ch
- Ethernet AVB 1.0-compatible MAC built in Interface: RGMII / Ethernet AVB (802.1BA)
- SYS-DMAC x 48 ch, Realtime-DMAC x 16 ch,
- Audio-DMAC x 32 ch, Audio(peripheral)-DMAC x 29 ch
- 32bit timer x 26 ch
- PWM timer × 7 ch
- I2C bus interface × 7 ch
- Serial communication interface (SCIF) × 11 ch
- Quad serial peripheral interface (QSPI) x 2 ch (for boot, HyperFlash support)
- Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
- Ethernet controller (IEEE802.3u, RMII, without PHY)
- Digital radio interface (DRIF) × 4 ch
Graphics
Integrated Graphics Information
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Features
[Edit/Modify Supported Features]
Supported ARM Extensions & Processor Features
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Block Diagram
Die Shot
- 16 nm process, CMOS FinFET
- 12.94 mm × 8.61 mm
- 111.36 mm² die size
References
- Takahashi, Chikafumi, et al. "4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10− 7 random hardware failures per hour reliability." Solid-State Circuits Conference (ISSCC), 2016 IEEE International. IEEE, 2016.
Facts about "R-Car H3 (SiP) - Renesas"
has ecc memory support | false + |
integrated gpu | PowerVR GX6650 + |
integrated gpu designer | Imagination Technologies + |
l1$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l1d$ size | 288 KiB (294,912 B, 0.281 MiB) + |
l1i$ size | 352 KiB (360,448 B, 0.344 MiB) + |
l2$ size | 2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) + |
max memory bandwidth | 47.68 GiB/s (48,824.32 MiB/s, 51.196 GB/s, 51,196.01 MB/s, 0.0466 TiB/s, 0.0512 TB/s) + |
max memory channels | 4 + |
supported memory type | LPDDR4-3200 + |