Difference between revisions of "renesas/r-car/m3 (sip)"

Revision as of 04:46, 23 July 2017

Template:mpu R-Car M3 is a 64-bit hepta-core ARM SoC designed by Renesas for the automotive industry and introduced in 2016. The M3 incorporates four Cortex-A53 cores, two Cortex-A57, and an additional Cortex-R7 core for real-time processing. This chip supports up to dual-channel LPDDR4-3200 memory. This chip incorporates the Imagination's PowerVR GX6250 GPU.

This model is an SiP variant of the M3 which include the DDR memory on-package.

Cache

Main articles: Cortex-A53 § Cache and Cortex-A57 § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

480 KiB

491,520 B
0.469 MiB

L1I$	256 KiB 262,144 B 0.25 MiB	2x48+5x32 KiB
L1D$	224 KiB 229,376 B 0.219 MiB	7x32 KiB

L2$

1.5 MiB

1,536 KiB
1,572,864 B
0.00146 GiB

Memory controller

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	LPDDR4-3200
Supports ECC	No
Controllers	1
Channels	2
Width	32 bit
Max Bandwidth	11.92 GiB/s 12,206.08 MiB/s 12.799 GB/s 12,799.003 MB/s 0.0116 TiB/s 0.0128 TB/s
Bandwidth	Single 5.96 GiB/s Double 11.92 GiB/s

Expansions

USB 3.0 host interface (DRD) × 1 port (wPHY)
USB 2.0 host interface × 1 port (wPHY)
USB 2.0 host/function/OTG interface × 1 port (wPHY)
SD host interface × 4 ch (SDR104)
Multimedia card interface × 2 ch
PCI Express 2.0 (1 lane) x 2 ch
Media local bus (MLB) interface × 1 ch (3-pin interface)
Controller area network (CAN-FD support) interface × 2ch
Ethernet AVB 1.0-compatible MAC built in Interface: RGMII / Ethernet AVB (802.1BA)
I2C bus interface × 8 ch
Serial communication interface (SCIF) × 11 ch
SPI multi I/O bus controller (RPC) × 1 ch (HyperFlashTM/QSPI support)
Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
Digital radio interface (DRIF) × 4 ch

Graphics

[Edit/Modify IGP Info]

Integrated Graphics Information

GPU	PowerVR GX6250
Designer	Imagination Technologies

Features

[Edit/Modify Supported Features]

Supported ARM Extensions & Processor Features

@@ Line 32: / Line 32: @@
 |package module 1={{packages/renesas/fcbga-1255}}
 }}
-'''R-Car M3''' is a {{arch|64}} [[hepta-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The M3 incorporates four {{armh|Cortex-A53}} cores, two {{armh|Cortex-A57}}, and an additional {{armh|Cortex-R7}} core for real-time processing. This chip supports up to dual-channel LPDDR4-3200 memory.
+'''R-Car M3''' is a {{arch|64}} [[hepta-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The M3 incorporates four {{armh|Cortex-A53}} cores, two {{armh|Cortex-A57}}, and an additional {{armh|Cortex-R7}} core for real-time processing. This chip supports up to dual-channel LPDDR4-3200 memory.  This chip incorporates the [[imagination technologies|Imagination]]'s {{imgtec|PowerVR GX6250}} [[GPU]].
 This model is an [[SiP]] variant of the {{\\|M3}} which include the DDR memory on-package.
@@ Line 58: / Line 58: @@
 |bandwidth dchan=11.92 GiB/s
 }}
+== Expansions ==
+* USB 3.0 host interface (DRD) × 1 port (wPHY)
+* USB 2.0 host interface × 1 port (wPHY)
+* USB 2.0 host/function/OTG interface × 1 port (wPHY)
+* SD host interface × 4 ch (SDR104)
+* Multimedia card interface × 2 ch
+* PCI Express 2.0 (1 lane) x 2 ch
+* Media local bus (MLB) interface × 1 ch (3-pin interface)
+* Controller area network (CAN-FD support) interface × 2ch
+* Ethernet AVB 1.0-compatible MAC built in Interface: RGMII / Ethernet AVB (802.1BA)
+* I2C bus interface × 8 ch
+* Serial communication interface (SCIF) × 11 ch
+* SPI multi I/O bus controller (RPC) × 1 ch (HyperFlashTM/QSPI support)
+* Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
+* Digital radio interface (DRIF) × 4 ch
+== Graphics ==
+{{integrated graphics
+| gpu                 = PowerVR GX6250
+| designer            = Imagination Technologies
+}}
+== Features ==
+{{arm features}}

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	R-Car M3 (SiP) - Renesas#package +
core count	7 +
core name	Cortex-A53 +, Cortex-A57 + and Cortex-R7 +
core voltage	0.9 V (9 dV, 90 cV, 900 mV) +
designer	ARM Holdings + and Renesas +
family	R-Car +
first announced	October 19, 2016 +
first launched	October 2016 +
full page name	renesas/r-car/m3 (sip) +
has ecc memory support	false +
instance of	microprocessor +
integrated gpu	PowerVR GX6250 +
integrated gpu designer	Imagination Technologies +
io voltage	3.3 V (33 dV, 330 cV, 3,300 mV) +
isa	ARMv8 +
isa family	ARM +
l1$ size	480 KiB (491,520 B, 0.469 MiB) +
l1d$ size	224 KiB (229,376 B, 0.219 MiB) +
l1i$ size	256 KiB (262,144 B, 0.25 MiB) +
l2$ size	1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
ldate	October 2016 +
main image	+
manufacturer	TSMC +
market segment	Embedded +
max cpu count	1 +
max memory bandwidth	11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels	2 +
microarchitecture	Cortex-A53 +, Cortex-A57 + and Cortex-R7 +
model number	M3 (SiP) +
name	R-Car M3 (SiP) +
package	FCBGA-1255 +
part number	R8J77960 +
process	16 nm (0.016 μm, 1.6e-5 mm) +
series	3rd Gen +
smp max ways	1 +
supported memory type	LPDDR4-3200 +
technology	CMOS +
thread count	7 +
word size	64 bit (8 octets, 16 nibbles) +

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