Semiconductor & Computer Engineering
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Difference between revisions of "renesas/r-car/v2h"
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{{memory controller | {{memory controller | ||
|type=DDR3-1600 | |type=DDR3-1600 | ||
| − | |ecc= | + | |ecc=Yes |
|controllers=1 | |controllers=1 | ||
|channels=1 | |channels=1 | ||
Revision as of 03:56, 23 July 2017
Template:mpu R-Car V2H is high-performance embedded 64-bit dual-core arm SoC designed by Renesas for the automotive industry and introduced in 2014. The V2H has two Cortex-A15 cores operating at 1 GHz and incorporates the Imagination PowerVR SGX531 GPU. This SoC supports up to DDR3-1600 memory.
Cache
- Main article: Cortex-A15 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Facts about "R-Car V2H - Renesas"
| has ecc memory support | true + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| max memory bandwidth | 5.96 GiB/s (6,103.04 MiB/s, 6.4 GB/s, 6,399.501 MB/s, 0.00582 TiB/s, 0.0064 TB/s) + |
| max memory channels | 1 + |
| supported memory type | DDR3-1600 + |