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Difference between revisions of "renesas/r-car/v2h"
< renesas‎ | r-car

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{{memory controller
 
{{memory controller
 
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|ecc=Yes
 
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|controllers=1
 
|channels=1
 
|channels=1

Revision as of 03:56, 23 July 2017

Template:mpu R-Car V2H is high-performance embedded 64-bit dual-core arm SoC designed by Renesas for the automotive industry and introduced in 2014. The V2H has two Cortex-A15 cores operating at 1 GHz and incorporates the Imagination PowerVR SGX531 GPU. This SoC supports up to DDR3-1600 memory.

Cache

Main article: Cortex-A15 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB  
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB  
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
     

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1600
Supports ECCYes
Controllers1
Channels1
Width32 bit
Max Bandwidth5.96 GiB/s
6,103.04 MiB/s
6.4 GB/s
6,399.501 MB/s
0.00582 TiB/s
0.0064 TB/s
Bandwidth
Single 5.96 GiB/s
Retrieved from "https://en.wikichip.org/w/index.php?title=renesas/r-car/v2h&oldid=56045"
Facts about "R-Car V2H - Renesas"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
R-Car V2H - Renesas#package +
base frequency1,000 MHz (1 GHz, 1,000,000 kHz) +
core count2 +
core nameCortex-A15 +
core voltage1.03 V (10.3 dV, 103 cV, 1,030 mV) +
designerRenesas + and ARM Holdings +
familyR-Car +
first announcedAugust 28, 2014 +
first launchedOctober 2016 +
full page namerenesas/r-car/v2h +
has ecc memory supporttrue +
instance ofmicroprocessor +
integrated gpuPowerVR SGX531 +
integrated gpu designerImagination Technologies +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
isaARMv8 +
isa familyARM +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldateOctober 2016 +
main imageFile:r-car v2h.jpg +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory bandwidth5.96 GiB/s (6,103.04 MiB/s, 6.4 GB/s, 6,399.501 MB/s, 0.00582 TiB/s, 0.0064 TB/s) +
max memory channels1 +
microarchitectureCortex-A15 +
model numberV2H +
nameR-Car V2H +
packageFCBGA-64 +
part numberR8A7792 +
process28 nm (0.028 μm, 2.8e-5 mm) +
series2nd Gen +
smp max ways1 +
supported memory typeDDR3-1600 +
technologyCMOS +
thread count2 +
word size64 bit (8 octets, 16 nibbles) +