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Difference between revisions of "renesas/r-car/h3 (sip)"
< renesas‎ | r-car

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{{renesas title|R-Car H3 (SiP)}}
 
{{renesas title|R-Car H3 (SiP)}}
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{{mpu}}
+
{{mpu
 +
|name=R-Car H3 (SiP)
 +
|image=r-car h3 (sip).png
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|image size=125px
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|designer=Renesas
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|designer 2=ARM Holdings
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|manufacturer=TSMC
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|model number=H3 (SiP)
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|part number=R8J77950
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|market=Embedded
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|first announced=December 2, 2015
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|first launched=March, 2018
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|family=R-Car
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|series=3rd Gen
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|isa=ARMv8
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|isa family=ARM
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|microarch=Cortex-A53
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|microarch 2=Cortex-A57
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|microarch 3=Cortex-R7
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|core name=Cortex-A53
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|core name 2=Cortex-A57
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|core name 3=Cortex-R7
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|process=16 nm
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|technology=CMOS
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|word size=64 bit
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|core count=9
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|thread count=9
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|max cpus=1
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|v core=0.8 V
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|v io=3.3 V
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|package module 1={{packages/renesas/fcbga-1255}}
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}}
 
'''R-Car H3''' is a {{arch|64}} [[nona-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The H3 incorporates four {{armh|Cortex-A57}} cores, four {{armh|Cortex-A53}} cores, and a single {{armh|Cortex-R7}} core for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory.
 
'''R-Car H3''' is a {{arch|64}} [[nona-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The H3 incorporates four {{armh|Cortex-A57}} cores, four {{armh|Cortex-A53}} cores, and a single {{armh|Cortex-R7}} core for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory.
  
 
This model is an [[SiP]] variant of the {{\\|H3}} which include the DDR memory on-package.
 
This model is an [[SiP]] variant of the {{\\|H3}} which include the DDR memory on-package.

Revision as of 03:13, 23 July 2017

Template:mpu R-Car H3 is a 64-bit nona-core ARM SoC designed by Renesas for the automotive industry and introduced in 2016. The H3 incorporates four Cortex-A57 cores, four Cortex-A53 cores, and a single Cortex-R7 core for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory.

This model is an SiP variant of the H3 which include the DDR memory on-package.

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