From WikiChip
Difference between revisions of "renesas/r-car/m2"
< renesas‎ | r-car

Line 33: Line 33:
 
|package module 1={{packages/renesas/fcbga-831}}
 
|package module 1={{packages/renesas/fcbga-831}}
 
}}
 
}}
 +
'''R-Car M2''' is a mid-range performance embedded [[tri-core]] SoC designed by [[Renesas]] for the automotive industry and introduced in late 2013. The M2 incorporates two {{armh|Cortex-A15}} cores operating at 1.5 GHz and a third {{renesas|SH-4A}} core for real-time processing. This chip incorporates [[imagination technologies|Imagination]]'s {{imgtec|PowerVR SGX544}} [[GPU]] operating at 520 MHz and supports up to dual-channel DDR3-1600 memory.
 +
 +
== Cache ==
 +
{{main|arm holdings/microarchitectures/cortex-a15#Memory_Hierarchy|l1=Cortex-A15 § Cache}}
 +
{{cache size
 +
|l1 cache=192 KiB
 +
|l1i cache=96 KiB
 +
|l1i break=3x32 KiB
 +
|l1d cache=96 KiB
 +
|l1d break=3x32 KiB
 +
|l2 cache=2 MiB
 +
|l2 break=1x2 MiB
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR3-1600
 +
|ecc=No
 +
|controllers=1
 +
|channels=2
 +
|width=32 bit
 +
|max bandwidth=11.92 GiB/s
 +
|bandwidth schan=5.96 GiB/s
 +
|bandwidth dchan=11.92 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
* Flash ROM and SRAM, Data bus width: 8 or 16 bits
 +
* PCI Express2.0 (1 lane)
 +
* USB 3.0 host interface × 1 port (wPHY)
 +
* USB 2.0 host interface × 2 ports (wPHY)
 +
* SD host interface × 3 ch (SDXC, UHS-I)
 +
* Multimedia card interface × 1 ch
 +
* Serial ATA interface × 2 ch
 +
* I²C bus interface × 9 ch
 +
* Serial communication interface (SCIF) × 18 ch
 +
* Quad serial peripheral interface (QSPI) × 1 ch (for boot)
 +
* Clock-synchronized serial interface (MSIOF) × 3 ch (SPI/IIS)
 +
* Ethernet AVB controller (IEEE802.1BA/802.1AS/802.1Qav/IEEE1722, GMII/MII, without PHY)
 +
* Ethernet controller (IEEE802.3u, RMII, without PHY)
 +
 +
== Graphics ==
 +
{{integrated graphics
 +
| gpu                = PowerVR SGX544
 +
| designer            = Imagination Technologies
 +
| execution units    = 2
 +
| max displays        = 2
 +
| frequency          = 520 MHz
 +
}}
 +
 +
== Features ==
 +
{{arm features
 +
|thumb=No
 +
|thumb2=Yes
 +
|thumbee=Yes
 +
|vfpv1=No
 +
|vfpv2=No
 +
|vfpv3=No
 +
|vfpv3-d16=No
 +
|vfpv3-f16=No
 +
|vfpv4=Yes
 +
|vfpv4-d16=No
 +
|vfpv5=No
 +
|neon=Yes
 +
|jazelle=No
 +
|wmmx=No
 +
|wmmx2=No
 +
}}
 +
 +
== Block Diagram ==
 +
::[[File:r-car m2 block.png|750px]]

Revision as of 16:22, 22 July 2017

Template:mpu R-Car M2 is a mid-range performance embedded tri-core SoC designed by Renesas for the automotive industry and introduced in late 2013. The M2 incorporates two Cortex-A15 cores operating at 1.5 GHz and a third SH-4A core for real-time processing. This chip incorporates Imagination's PowerVR SGX544 GPU operating at 520 MHz and supports up to dual-channel DDR3-1600 memory.

Cache

Main article: Cortex-A15 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$192 KiB
196,608 B
0.188 MiB
L1I$96 KiB
98,304 B
0.0938 MiB
3x32 KiB  
L1D$96 KiB
98,304 B
0.0938 MiB
3x32 KiB  
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB  

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1600
Supports ECCNo
Controllers1
Channels2
Width32 bit
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 5.96 GiB/s
Double 11.92 GiB/s

Expansions

  • Flash ROM and SRAM, Data bus width: 8 or 16 bits
  • PCI Express2.0 (1 lane)
  • USB 3.0 host interface × 1 port (wPHY)
  • USB 2.0 host interface × 2 ports (wPHY)
  • SD host interface × 3 ch (SDXC, UHS-I)
  • Multimedia card interface × 1 ch
  • Serial ATA interface × 2 ch
  • I²C bus interface × 9 ch
  • Serial communication interface (SCIF) × 18 ch
  • Quad serial peripheral interface (QSPI) × 1 ch (for boot)
  • Clock-synchronized serial interface (MSIOF) × 3 ch (SPI/IIS)
  • Ethernet AVB controller (IEEE802.1BA/802.1AS/802.1Qav/IEEE1722, GMII/MII, without PHY)
  • Ethernet controller (IEEE802.3u, RMII, without PHY)

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR SGX544
DesignerImagination Technologies
Execution Units2Max Displays2
Frequency520 MHz
0.52 GHz
520,000 KHz

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
Thumb-2Thumb-2 Extension
ThumbEEThumb Execution Environment Extension
VFPv4Vector Floating Point (VFP) v4 Extension
NEONAdvanced SIMD extension

Block Diagram

r-car m2 block.png
Retrieved from "https://en.wikichip.org/w/index.php?title=renesas/r-car/m2&oldid=55850"
Facts about "R-Car M2 - Renesas"
RDF feed
has ecc memory supportfalse +
integrated gpuPowerVR SGX544 +
integrated gpu base frequency520 MHz (0.52 GHz, 520,000 KHz) +
integrated gpu designerImagination Technologies +
integrated gpu execution units2 +
l1$ size192 KiB (196,608 B, 0.188 MiB) +
l1d$ size96 KiB (98,304 B, 0.0938 MiB) +
l1i$ size96 KiB (98,304 B, 0.0938 MiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels2 +
supported memory typeDDR3-1600 +