Semiconductor & Computer Engineering
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Difference between revisions of "renesas/r-car/m1a"
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| − | '''R-Car M1A''' is a mid-range performance embedded [[dual-core]] SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. The M1A features a single {{armh|Cortex-A9|l=arch}} core and an additional {{renesas|SH-4A|l=arch}} core, both operating at 800 MHz. This SoC supports up to 1 GiB of dual-channel DDR3-1066 memory. | + | '''R-Car M1A''' is a mid-range performance embedded [[dual-core]] SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. The M1A features a single {{armh|Cortex-A9|l=arch}} core and an additional {{renesas|SH-4A|l=arch}} core, both operating at 800 MHz. This chip incorporates [[Imagination]]'s {{imgtec|PowerVR SGX540}} [[GPU]] operating at 200 MHz. This SoC supports up to 1 GiB of dual-channel DDR3-1066 memory. |
== Cache == | == Cache == | ||
Revision as of 11:08, 21 July 2017
Template:mpu R-Car M1A is a mid-range performance embedded dual-core SoC for the automotive industry designed by Renesas and introduced in 2011. The M1A features a single Cortex-A9 core and an additional SH-4A core, both operating at 800 MHz. This chip incorporates Imagination's PowerVR SGX540 GPU operating at 200 MHz. This SoC supports up to 1 GiB of dual-channel DDR3-1066 memory.
Cache
- Main article: Cortex-A9 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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- MLB (MOST150) 6-Pin I/F
- 2 x CAN 32 Message Buffers
- MMC
- 3 x SD
Graphics
- 20MPoly/s; 1000MPix/s; 3.2GFlops/s
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Integrated Graphics Information
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Features
[Edit/Modify Supported Features]
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Supported ARM Extensions & Processor Features
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Block Diagram
Facts about "R-Car M1A - Renesas"
| has ecc memory support | false + |
| integrated gpu | PowerVR SGX540 + |
| integrated gpu base frequency | 200 MHz (0.2 GHz, 200,000 KHz) + |
| integrated gpu designer | Imagination Technologies + |
| integrated gpu execution units | 2 + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| max memory bandwidth | 7.95 GiB/s (8,140.8 MiB/s, 8.536 GB/s, 8,536.248 MB/s, 0.00776 TiB/s, 0.00854 TB/s) + |
| max memory channels | 2 + |
| supported memory type | DDR3-1066 + and DDR2-800 + |