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Difference between revisions of "renesas/r-car/m1a"
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'''R-Car M1A''' is a mid-range performance embedded [[dual-core]] SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. The M1A features a single {{armh|Cortex-A9|l=arch}} core and an additional {{renesas|SH-4A|l=arch}} core, both operating at 800 MHz. This SoC supports up to 1 GiB of dual-channel DDR3-1066 memory.
 
'''R-Car M1A''' is a mid-range performance embedded [[dual-core]] SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. The M1A features a single {{armh|Cortex-A9|l=arch}} core and an additional {{renesas|SH-4A|l=arch}} core, both operating at 800 MHz. This SoC supports up to 1 GiB of dual-channel DDR3-1066 memory.
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 +
== Cache ==
 +
{{main|arm holdings/microarchitectures/cortex-a9#Memory_Hierarchy|l1=Cortex-A9 § Cache}}
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{{cache size
 +
|l1 cache=128 KiB
 +
|l1i cache=64 KiB
 +
|l1i break=2x32 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=64 KiB
 +
|l1d break=2x32 KiB
 +
|l1d desc=4-way set associative
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR3-1066
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|type=DDR2-800
 +
|ecc=No
 +
|max mem=1 GiB
 +
|controllers=1
 +
|channels=2
 +
|width=32 bit
 +
|max bandwidth=7.95 GiB/s
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|bandwidth schan=3.97 GiB/s
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|bandwidth dchan=7.95 GiB/s
 +
}}
 +
 +
== Expansions ==
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{{expansions
 +
| usb revision      = 2.0
 +
| usb ports          = 2
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| usb rate          = 480 Mbps
 +
| uart              = Yes
 +
| uart ports        = 8
 +
| sata revision      = 3.0
 +
| sata ports        = 1
 +
| i2c                = Yes
 +
| i2c ports          = 4
 +
| gp io              = Yes
 +
| jtag              = Yes
 +
}}
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* MLB (MOST150) 6-Pin I/F
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* 2 x CAN 32 Message Buffers
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* MMC
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* 3 x SD
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== Graphics ==
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* 20MPoly/s; 1000MPix/s; 3.2GFlops/s
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{{integrated graphics
 +
| gpu                = PowerVR SGX540
 +
| designer            = Imagination Technologies
 +
| execution units    = 2
 +
| max displays        = 2
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| frequency          = 200 MHz
 +
 +
| opengl es ver      = 2.0
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| opengl ver          = 2.1
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}}
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== Features ==
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{{arm features
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|thumb=No
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|thumb2=Yes
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|thumbee=Yes
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|vfpv1=No
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|vfpv2=No
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|vfpv3=Yes
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|vfpv3-d16=No
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|vfpv3-f16=No
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|vfpv4=No
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|vfpv4-d16=No
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|vfpv5=No
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|neon=Yes
 +
|jazelle=Yes
 +
|wmmx=No
 +
|wmmx2=No
 +
}}

Revision as of 10:18, 21 July 2017

Template:mpu R-Car M1A is a mid-range performance embedded dual-core SoC for the automotive industry designed by Renesas and introduced in 2011. The M1A features a single Cortex-A9 core and an additional SH-4A core, both operating at 800 MHz. This SoC supports up to 1 GiB of dual-channel DDR3-1066 memory.

Cache

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB4-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB4-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-800
Supports ECCNo
Max Mem1 GiB
Controllers1
Channels2
Width32 bit
Max Bandwidth7.95 GiB/s
8,140.8 MiB/s
8.536 GB/s
8,536.248 MB/s
0.00776 TiB/s
0.00854 TB/s
Bandwidth
Single 3.97 GiB/s
Double 7.95 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0
Ports2
Rate480 Mbps
UART
Ports8
SATA
Revision3.0
Ports1
I²C
Ports4
GP I/OYes
JTAGYes
  • MLB (MOST150) 6-Pin I/F
  • 2 x CAN 32 Message Buffers
  • MMC
  • 3 x SD

Graphics

  • 20MPoly/s; 1000MPix/s; 3.2GFlops/s

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR SGX540
DesignerImagination Technologies
Execution Units2Max Displays2
Frequency200 MHz
0.2 GHz
200,000 KHz
Standards
OpenGL2.1
OpenGL ES2.0

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
Thumb-2Thumb-2 Extension
ThumbEEThumb Execution Environment Extension
VFPv3Vector Floating Point (VFP) v3 Extension
NEONAdvanced SIMD extension
JazelleDirect Bytecode eXecution
Retrieved from "https://en.wikichip.org/w/index.php?title=renesas/r-car/m1a&oldid=55621"
Facts about "R-Car M1A - Renesas"
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"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
R-Car M1A - Renesas#package +
base frequency800 MHz (0.8 GHz, 800,000 kHz) +
core count2 +
core nameCortex-A9 + and SH-4A +
core voltage1.2 V (12 dV, 120 cV, 1,200 mV) +
designerRenesas + and ARM Holdings +
familyR-Car +
first announcedFebruary 16, 2011 +
first launchedJune 2012 +
full page namerenesas/r-car/m1a +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuPowerVR SGX540 +
integrated gpu base frequency200 MHz (0.2 GHz, 200,000 KHz) +
integrated gpu designerImagination Technologies +
integrated gpu execution units2 +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
isaARMv7 + and SuperH +
isa familyARM + and SuperH +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description4-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
ldateJune 2012 +
manufacturerTSMC +
market segmentEmbedded +
max memory1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) +
max memory bandwidth7.95 GiB/s (8,140.8 MiB/s, 8.536 GB/s, 8,536.248 MB/s, 0.00776 TiB/s, 0.00854 TB/s) +
max memory channels2 +
microarchitectureCortex-A9 + and SH-4A +
model numberM1A +
nameR-Car M1A +
packageFCBGA-472 +
part numberR8A77781 +
process40 nm (0.04 μm, 4.0e-5 mm) +
release price$ 70.00 (€ 63.00, £ 56.70, ¥ 7,233.10) +
series1st Gen +
supported memory typeDDR2-800 + and DDR3-1066 +
technologyCMOS +
thread count2 +
word size32 bit (4 octets, 8 nibbles) +