From WikiChip
Difference between revisions of "amd/microarchitectures/vega"
m (→Key changes from {{\\|graphics core next 4th gen(Vega)}}) |
|||
Line 21: | Line 21: | ||
[[File:amd gpu roadmap.png|400px|right]] | [[File:amd gpu roadmap.png|400px|right]] | ||
− | === Key changes from {{\\|graphics core next 4th gen | + | === Key changes from {{\\|graphics core next 4th gen}} === |
* High Bandwidth Cache Controller | * High Bandwidth Cache Controller | ||
* HBM 2 | * HBM 2 |
Revision as of 03:28, 21 July 2017
Edit Values | |
GCN 5th gen µarch | |
General Info | |
Arch Type | GPU |
Designer | AMD |
Manufacturer | GlobalFoundries |
Introduction | 2017 |
Process | 14 nm |
Succession | |
Graphics core next 5th gen (also known as Vega) is a planned microarchitecture being developed by AMD as a successor to GCN 4th gen.
Architecture
Key changes from graphics core next 4th gen
- High Bandwidth Cache Controller
- HBM 2
References
- AMD 2017 Financial Analyst Day, May 16, 2017
See Also
Facts about "Vega - Microarchitectures - AMD"
codename | Vega + |
designer | AMD + |
first launched | 2017 + |
full page name | amd/microarchitectures/vega + |
instance of | microarchitecture + |
manufacturer | GlobalFoundries + |
microarchitecture type | GPU + |
name | Vega + |
process | 12 nm (0.012 μm, 1.2e-5 mm) + |