Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/core i5/i5-6440eq"
| Line 9: | Line 9: | ||
|s-spec=SR2DU | |s-spec=SR2DU | ||
|market=Embedded | |market=Embedded | ||
| + | |first announced=October 12, 2015 | ||
| + | |first launched=October 12, 2015 | ||
| + | |release price=$250.00 | ||
|family=Core i5 | |family=Core i5 | ||
|series=i5-6000 | |series=i5-6000 | ||
| Line 33: | Line 36: | ||
|word size=64 bit | |word size=64 bit | ||
|core count=4 | |core count=4 | ||
| − | |thread count= | + | |thread count=4 |
|max cpus=1 | |max cpus=1 | ||
| + | |max memory=64 GiB | ||
| + | |v core min=0.55 V | ||
| + | |v core max=1.52 V | ||
|tdp=45 W | |tdp=45 W | ||
|tjunc min=0 °C | |tjunc min=0 °C | ||
Revision as of 23:23, 7 July 2017
Template:mpu Core i5-6440EQ is a 64-bit quad-core mid-range performance x86 mobile microprocessor introduced by Intel in late 2015. This processor, which is based on the Skylake microarchitecture, is manufactured on Intel's improved 14 nm process. The i5-6440EQ operates at 2.7 GHz with a TDP of 45 W and with a Turbo Boost frequency of 3.4 GHz for a single active core. This MPU supports up to 64 GiB of dual-channel non-ECC DDR4-2133 memory and incorporates Intel's HD Graphics 530 IGP operating at 350 MHz with a burst frequency of 1 GHz.
Cache
- Main article: Skylake § Cache
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||||||||||||||
|
|||||||||||||||||||||||||||||||||||||
Facts about "Core i5-6440EQ - Intel"
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |