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Difference between revisions of "intel/core i5/i5-6600"
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|tdp=65 W | |tdp=65 W | ||
|package module 1={{packages/intel/fclga-1151}} | |package module 1={{packages/intel/fclga-1151}} | ||
+ | }} | ||
+ | |||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=256 KiB | ||
+ | |l1i cache=128 KiB | ||
+ | |l1i break=4x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=128 KiB | ||
+ | |l1d break=4x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=1 MiB | ||
+ | |l2 break=4x256 KiB | ||
+ | |l2 desc=4-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=6 MiB | ||
+ | |l3 break=4x1.5 MiB | ||
+ | |l3 policy=write-back | ||
}} | }} |
Revision as of 03:09, 7 July 2017
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Core i5-6600 - Intel"
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |