From WikiChip
Difference between revisions of "cavium/octeon/cn3860-600bg1521-exp"
< cavium‎ | octeon

m (Bot: corrected param)
m (Bot: moving all {{mpu}} to {{chip}})
 
Line 1: Line 1:
 
{{cavium title|CN3860-600 EXP}}
 
{{cavium title|CN3860-600 EXP}}
−
{{mpu
+
{{chip
 
| name                = Cavium CN3860-600 EXP
 
| name                = Cavium CN3860-600 EXP
 
| no image            =  
 
| no image            =  

Latest revision as of 15:11, 13 December 2017

Edit Values
Cavium CN3860-600 EXP
octeon cn38xx.png
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN3860-600 EXP
Part NumberCN3860-600BG1521-EXP
MarketNetworking
IntroductionAugust 22, 2005 (announced)
August 22, 2005 (launched)
General Specs
FamilyOCTEON
SeriesCN3800
Frequency600 MHz
Microarchitecture
ISAMIPS64 (MIPS)
MicroarchitecturecnMIPS
Core NamecnMIPS
Process130 nm
TechnologyCMOS
Word Size64 bit
Cores16
Threads16
Max Memory16 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Packaging
PackageFCBGA-1521 (BGA)
Ball Count1521
InterconnectBGA-1521

The CN3860-600 EXP is a 64-bit hexadeca-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates sixteen cnMIPS cores, operates at 600 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.

Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$640 KiB
655,360 B
0.625 MiB
L1I$512 KiB
524,288 B
0.5 MiB
16x32 KiB64-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
16x8 KiB64-way set associativeWrite-through
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  1x1 MiB8-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-800
Supports ECCYes
Max Mem16 GiB
Controllers1
Channels1
Width128 bit
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 11.92 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI-X
Width64 bit
Clock133.33 MHz
Rate1,017.25 MiB/s
Featureshost or slave
UART
Ports2
GP I/OYes


Networking[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
RGMIIYes (Ports: 8)
SPI
SPI-4.2Yes (Ports: 2)

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
RegEx
RegExYes
Features16 Engines
Networking
TCPYes
QoSYes
Compression
CompressionYes
DecompressionYes

Block diagram[edit]

octeon cn38xx block diagram.png

Datasheet[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon/cn3860-600bg1521-exp&oldid=70248"
Facts about "CN3860-600 EXP - Cavium"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN3860-600 EXP - Cavium#package +
base frequency600 MHz (0.6 GHz, 600,000 kHz) +
core count16 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedAugust 22, 2005 +
first launchedAugust 22, 2005 +
full page namecavium/octeon/cn3860-600bg1521-exp +
has ecc memory supporttrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for regular expressiontrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size640 KiB (655,360 B, 0.625 MiB) +
l1d$ description64-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description64-way set associative +
l1i$ size512 KiB (524,288 B, 0.5 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldateAugust 22, 2005 +
main imageFile:octeon cn38xx.png +
manufacturerTSMC +
market segmentNetworking +
max cpu count1 +
max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3860-600 EXP +
nameCavium CN3860-600 EXP +
packageFCBGA-1521 +
part numberCN3860-600BG1521-EXP +
process130 nm (0.13 μm, 1.3e-4 mm) +
seriesCN3800 +
smp max ways1 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count16 +
word size64 bit (8 octets, 16 nibbles) +