Semiconductor & Computer Engineering
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Difference between revisions of "amd/k5/amd-k5-pr75abr"
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Latest revision as of 15:08, 13 December 2017
| Edit Values | |
| AMD-K5-PR75ABR | |
| General Info | |
| Designer | AMD |
| Manufacturer | AMD |
| Model Number | AMD-K5-PR75ABR |
| Part Number | AMD-K5-PR75ABR |
| Market | Desktop |
| Introduction | 1996 (announced) October 7, 1996 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | K5 |
| Series | SSA/5 |
| Frequency | 75 MHz |
| Bus type | FSB |
| Bus speed | 50 MHz |
| Bus rate | 50 MT/s |
| Clock multiplier | 1.5 |
| CPUID | 501 |
| Microarchitecture | |
| Microarchitecture | K5 |
| Core Name | SSA/5 |
| Core Family | 5 |
| Core Model | 0 |
| Core Stepping | 1 |
| Process | 350 nm |
| Transistors | 4,300,000 |
| Technology | CMOS |
| Die | 161 mm² |
| Word Size | 32 bit |
| Cores | 1 |
| Threads | 1 |
| Max Memory | 4 GiB |
| Max Address Mem | 0xFFFFFFFF |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Power dissipation | 11.8 W |
| Vcore | 3.525 V ± 2% |
| Tcase | 0 °C – 70 °C |
| Tstorage | -65°C – 150 °C |
AMD-K5-PR75ABR was a 32-bit x86 microprocessor developed by AMD and released in 1996. This chip was sold as Pentium 75 MHz equivalent. The processor used AMD's 2nd revision of their K5 microarchitecture, operating at 75 MHz with a TDP of 11.8 W.
Contents
Cache[edit]
- Main article: K5 § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 4-way set associative |
| L1D$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative |
Die Shot[edit]
Graphics[edit]
This SoC has no integrated graphics processing unit.
Features[edit]
- P75 P-Rating
- Auto-power down state
- Stop clock state
See also[edit]
Facts about "AMD-K5-PR75ABR - AMD"
| l1d$ description | 4-way set associative + |
| l1d$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| processor p-rating | P75 + |