From WikiChip
Difference between revisions of "amd/am486/am486dx2-100"
m (Bot: corrected param) |
m (Bot: switching template from {{mpu}} to a more generic {{chip}}) |
||
Line 1: | Line 1: | ||
{{amd title|Am486DX2-100}} | {{amd title|Am486DX2-100}} | ||
− | {{ | + | {{chip |
| name = Am486DX2-100 | | name = Am486DX2-100 | ||
| image = | | image = |
Latest revision as of 14:18, 13 December 2017
Edit Values | |
Am486DX2-100 | |
General Info | |
Designer | AMD |
Manufacturer | AMD |
Model Number | Am486DX2-100 |
Part Number | A80486DX2-100 |
Market | Desktop |
Introduction | 1994 (announced) September, 1994 (launched) |
Shop | Amazon |
General Specs | |
Family | Am486 |
Series | Am486DX2 |
Frequency | 100 MHz |
Bus type | FSB |
Bus speed | 50 MHz |
Bus rate | 50 MT/s |
Clock multiplier | 2 |
Microarchitecture | |
Microarchitecture | 80486 |
Core Name | 486DX2 |
Process | 500 nm |
Transistors | 1,200,000 |
Technology | CMOS |
Word Size | 32 bit |
Cores | 1 |
Max Memory | 4 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
Vcore | 3.3 V ± 0.3 V |
OP Temperature | 0 °C – 85 °C |
Am486DX2-100 was an 80486-compatible microprocessor introduced by AMD in 1994. This processor had a clock multiplier of 2 having base frequency of 100 MHz with a bus frequency of 50 MHz.
Cache[edit]
- Main article: 80486 § Cache
Cache Info [Edit Values] | ||
L1$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative (unified, write-through policy) |
Graphics[edit]
This chip had no integrated graphics processing unit.
See also[edit]
Facts about "Am486DX2-100 - AMD"
l1$ description | 4-way set associative + |
l1$ size | 8 KiB (8,192 B, 0.00781 MiB) + |