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== Instruction Listing ==
 
== Instruction Listing ==
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The ARMv1 has 45 operations under 23 mnemonics. The ARMv1 is broken down into 8 classes of instruction:
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The ARMv1 ISA has 45 operations under 23 mnemonics. The ARMv1 is broken down into 8 classes of instruction:
  
 
* [[#movement_instructions|Movement Instructions]]
 
* [[#movement_instructions|Movement Instructions]]

Revision as of 18:53, 27 June 2017

ARMv1 is the first ARM instruction set version. Introduced with the ARM1 on April 26 1985, the ARMv1 defines a 32-bit ISA along with 26-bit addressing space. The ARMv1 was only implemented by the ARM1 and was replaced soon after by the ARM2. Only a few hundred of those chips were ever fabricated.

Overview

The ARMv1 is a simple architecture consisting of mostly simple operations along with a handful of complex ones. Each instruction is 32-bit in size and operates on two 32-bit operands. There is a 24-bit program counter allowing for a 26-bit address space of up to 64 MiB of memory.

Registers

There are 16 general purpose 32-bit registers. With the exception of register 15, all registers are orthogonal with no specific designated purpose.

Instruction Listing

The ARMv1 ISA has 45 operations under 23 mnemonics. The ARMv1 is broken down into 8 classes of instruction:

ARMv1 ISA
Mnemonic Syntax Description Action
Movement Instructions
Movement instructions move data between registers and operands.
MOVMOV<cond>{S} Rd, #immMove value immedRd = immed
MOVMOV<cond>{S} Rd, Rm, {, <shift>}Move valueRd = {shifted Rm}
MVNMVN<cond>{S} Rd, #immMove NOT value immedRd = ¬immed
MVNMVN<cond>{S} Rd, Rm, {, <shift>}Move NOT valueRd = ¬{shifted Rm}
Load Instructions
Load instructions move the content of memory addresses into registers.
LDMLDM<cond><type> Rn{!}, <reglist>{^}Load multipleaddr = Rn
for each Rd in {reglist}:
     Rd = [addr]
     update address based on {type}
LDRLDR<cond>{B} Rd, [Rn {, #imm}]{!}Load register immedRd = [Rn + imm]
If !: Rn = Rn + imm
LDRLDR<cond>{B} Rd, [Rn, Rm {, <shift>}]{!}Load registerRd = [Rn + {shifted Rm}]
If !: Rn = Rn + {shifted Rm}]
LDRLDR<cond>{B}{T} Rd, [Rn], #immLoad register, post indexRd = [Rn]
Rn = Rn + imm
LDRLDR<cond>{B}{T} Rd, [Rn], Rm {, <shift>}Load register, post indexRd = [Rn]
Rn = Rn + {shifted Rm}
Store Instructions
Store instructions moves the values from registers into memory.
STMSTM<cond><type> Rn{!}, <reglist>{^}Store multipleaddr = Rn
for each Rd in {reglist}:
     [addr] = Rd
     update address based on {type}
STRSTR<cond>{B} Rd, [Rn {, #imm}]{!}Store register immed[Rn + imm] = Rd
If !: Rn = Rn + imm
STRSTR<cond>{B} Rd, [Rn, Rm {, <shift>}]{!}Store register[Rn + {shifted Rm}] = Rd
If !: Rn = Rn + {shifted Rm}]
STRSTR<cond>{B}{T} Rd, [Rn], #immStore register, post index[Rn] = Rd
Rn = Rn + imm
STRSTR<cond>{B}{T} Rd, [Rn], Rm {, <shift>}Store register, post index[Rn] = Rd
Rn = Rn + {shifted Rm}
Arithmetic Instructions
Arithmetic instructions perform basic mathematical operations on two operands.
ADCADC<cond>{S} Rd, Rn, #immAdd and carry immedRd = Rn + imm + C
ADCADC<cond>{S} Rd, Rn, Rm{, <shift>}Add and carryRd = Rn + {shifted Rm} + C
ADDADD<cond>S Rd, Rn, #immAdd immedRd = Rn + imm
ADDADD<cond>S Rd, Rn, Rm{, <shift>}AddRd = Rn + {shifted Rm}
RSBRSB<cond>S Rd, Rn, #immReverse subtract immedRd = imm - Rn
RSBRSB<cond>S Rd, Rn, Rm{, <shift>}Reverse subtractRd = {shifted Rm} - Rn
RSCRSB<cond>S Rd, Rn, #immReverse subtract with carry immedRd = imm - Rn - ¬C
RSCRSB<cond>S Rd, Rn, Rm{, <shift>}Reverse subtract with carryRd = {shifted Rm} - Rn - ¬C
SBCSBC<cond>{S} Rd, Rn, #immSubtract with carry immedRd = Rn - imm - ¬C
SBCSBC<cond>{S} Rd, Rn, Rm{, <shift>}Subtract with carryRd = Rn - {shifted Rm} - ¬C
SUBSUB<cond>{S} Rd, Rn, #immSubtract immedRd = Rn - imm
SUBSUB<cond>{S} Rd, Rn, Rm{, <shift>}SubtractRd = Rn - {shifted Rm}
Logical Instructions
Logical instructions perform logical bitwise operations on operands.
ANDAND<cond>{S} Rd, Rn, #immAND immedRd = Rn & imm
ANDAND<cond>{S} Rd, Rn, Rm{, <shift>}ANDRd = Rn & {shifted Rm}
BICBIC<cond>{S} Rd, Rn, #immBit clear immedRd = Rn & ¬imm
BICBIC<cond>{S} Rd, Rn, Rm{, <shift>}Bit clearRd = Rn & ¬Rm
EOREOR<cond>{S} Rd, Rn, #immExclusive OR immedRd = Rn ⊕ imm
EOREOR<cond>{S} Rd, Rn, Rm{, <shift>}Exclusive ORRd = Rn ⊕ {shifted Rm}
ORRORR<cond>{S} Rd, Rn, #immLogical OR immedRd = Rn ∥ imm
ORRORR<cond>{S} Rd, Rn, Rm{, <shift>}Logical ORRd = Rn ∥ {shifted Rm}
Comparison Instructions
Comparison instructions compare two values and set appropriate status flags.
CMNCMN<cond> Rn, #immCompare negative immedCPSR flags set on (Rn + imm)
CMNCMN<cond> Rn, Rm{, <shift>}Compare negativeCPSR flags set on (Rn + {shifted Rm})
CMPCMP<cond> Rn, #immCompare immedCPSR flags set on (Rn - imm)
CMPCMP<cond> Rn, Rm{, <shift>}CompareCPSR flags set on (Rn - {shifted Rm})
TEQTEQ<cond> Rn, #immTest equality immedCPSR flags set on (Rn ⊕ imm)
TEQTEQ<cond> Rn, Rm{, <shift>}Test equalityCPSR flags set on (Rn ⊕ {shifted Rm})
TSTTST<cond> Rn, #immTest bits immedCPSR flags set on (Rn & imm)
TSTTST<cond> Rn, Rm{, <shift>}Test bitsCPSR flags set on (Rn & {shifted Rm})
Branch Instructions
Branch instructions order instruction processing to start elsewhere conditionally or unconditionally.
BB<cond> immBranch relativePC = PC + address
BLBL<cond> immBranch and link relativeLR = RET
PC = PC + address
Miscellaneous Instructions
Any instruction that doesn't belong anywhere else.
SWISWI<cond> immSoftware interruptLR = RET
Execute SWI vector in supervisor mode
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