Difference between revisions of "arm/armv1"

Revision as of 18:23, 27 June 2017

ARMv1 is the first ARM instruction set version. Introduced with the ARM1 on April 26 1985, the ARMv1 defines a 32-bit ISA along with 26-bit addressing space. The ARMv1 was only implemented by the ARM1 and was replaced soon after by the ARM2. Only a few hundred of those chips were ever fabricated.

Overview

The ARMv1 is a simple architecture. Each instruction is 32-bit in size and operates on two 32-bit operands. There is a program counter which is 26 bits in size allowing for an address space of up to 64 MiB of data.

Registers

There are 16 general purpose 32-bit registers. With the exception of register 15, all registers are orthogonal with no specific designated purpose.

Instruction Listing

The ARMv1 is broken down into 8 classes of instruction:

Movement Instructions
Load Instructions
Store Instructions
Arithmetic Instructions
Logical Instructions
Comparison Instructions
Branch Instructions
Miscellaneous Instructions

ARMv1 ISA
Mnemonic	Syntax	Description	Action
Movement Instructions
MOV	MOV<cond>{S} Rd, #imm	Move value immed	Rd = immed
MOV	MOV<cond>{S} Rd, Rm, {, <shift>}	Move value	Rd = {shifted Rm}
MVN	MVN<cond>{S} Rd, #imm	Move NOT value immed	Rd = ¬immed
MVN	MVN<cond>{S} Rd, Rm, {, <shift>}	Move NOT value	Rd = ¬{shifted Rm}
Load Instructions
LDM	LDM<cond><type> Rn{!}, <reglist>{^}	Load multiple	addr = Rn for each Rd in {reglist}: Rd = [addr] update address based on {type}
LDR	LDR<cond>{B} Rd, [Rn {, #imm}]{!}	Load register immed	Rd = [Rn + imm] If !: Rn = Rn + imm
LDR	LDR<cond>{B} Rd, [Rn, Rm {, <shift>}]{!}	Load register	Rd = [Rn + {shifted Rm}] If !: Rn = Rn + {shifted Rm}]
LDR	LDR<cond>{B}{T} Rd, [Rn], #imm	Load register, post index	Rd = [Rn] Rn = Rn + imm
LDR	LDR<cond>{B}{T} Rd, [Rn], Rm {, <shift>}	Load register, post index	Rd = [Rn] Rn = Rn + {shifted Rm}
Store Instructions
STM	STM<cond><type> Rn{!}, <reglist>{^}	Store multiple	addr = Rn for each Rd in {reglist}: [addr] = Rd update address based on {type}
STR	STR<cond>{B} Rd, [Rn {, #imm}]{!}	Store register immed	[Rn + imm] = Rd If !: Rn = Rn + imm
STR	STR<cond>{B} Rd, [Rn, Rm {, <shift>}]{!}	Store register	[Rn + {shifted Rm}] = Rd If !: Rn = Rn + {shifted Rm}]
STR	STR<cond>{B}{T} Rd, [Rn], #imm	Store register, post index	[Rn] = Rd Rn = Rn + imm
STR	STR<cond>{B}{T} Rd, [Rn], Rm {, <shift>}	Store register, post index	[Rn] = Rd Rn = Rn + {shifted Rm}
Arithmetic Instructions
ADC	ADC<cond>{S} Rd, Rn, #imm	Add and carry immed	Rd = Rn + imm + C
ADC	ADC<cond>{S} Rd, Rn, Rm{, <shift>}	Add and carry	Rd = Rn + {shifted Rm} + C
ADD	ADD<cond>S Rd, Rn, #imm	Add immed	Rd = Rn + imm
ADD	ADD<cond>S Rd, Rn, Rm{, <shift>}	Add	Rd = Rn + {shifted Rm}
RSB	RSB<cond>S Rd, Rn, #imm	Reverse subtract immed	Rd = imm - Rn
RSB	RSB<cond>S Rd, Rn, Rm{, <shift>}	Reverse subtract	Rd = {shifted Rm} - Rn
RSC	RSB<cond>S Rd, Rn, #imm	Reverse subtract with carry immed	Rd = imm - Rn - ¬C
RSC	RSB<cond>S Rd, Rn, Rm{, <shift>}	Reverse subtract with carry	Rd = {shifted Rm} - Rn - ¬C
SBC	SBC<cond>{S} Rd, Rn, #imm	Subtract with carry immed	Rd = Rn - imm - ¬C
SBC	SBC<cond>{S} Rd, Rn, Rm{, <shift>}	Subtract with carry	Rd = Rn - {shifted Rm} - ¬C
Logical Instructions
AND	AND<cond>{S} Rd, Rn, #imm	AND immed	Rd = Rn & imm
AND	AND<cond>{S} Rd, Rn, Rm{, <shift>}	AND	Rd = Rn & {shifted Rm}
BIC	BIC<cond>{S} Rd, Rn, #imm	Bit clear immed	Rd = Rn & ¬imm
BIC	BIC<cond>{S} Rd, Rn, Rm{, <shift>}	Bit clear	Rd = Rn & ¬Rm
EOR	EOR<cond>{S} Rd, Rn, #imm	Exclusive OR immed	Rd = Rn ⊕ imm
EOR	EOR<cond>{S} Rd, Rn, Rm{, <shift>}	Exclusive OR	Rd = Rn ⊕ {shifted Rm}
ORR	ORR<cond>{S} Rd, Rn, #imm	Logical OR immed	Rd = Rn ∥ imm
ORR	ORR<cond>{S} Rd, Rn, Rm{, <shift>}	Logical OR	Rd = Rn ∥ {shifted Rm}
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Comparison Instructions
CMN	CMN<cond> Rn, #imm	Compare negative immed	CPSR flags set on (Rn + imm)
CMN	CMN<cond> Rn, Rm{, <shift>}	Compare negative	CPSR flags set on (Rn + {shifted Rm})
CMP	CMP<cond> Rn, #imm	Compare immed	CPSR flags set on (Rn - imm)
CMP	CMP<cond> Rn, Rm{, <shift>}	Compare	CPSR flags set on (Rn - {shifted Rm})
Branch Instructions
B	B<cond> #imm	Branch relative	PC = PC + address
BL	BL<cond> #imm	Branch and link relative	LR = RET PC = PC + address
Miscellaneous Instructions

@@ Line 37: / Line 37: @@
 {{inst|mn=LDM  |col 1=LDM<cond><type> Rn{!}, <reglist>{^} |col 2= Load multiple |col 3 = addr = Rn<br>for each Rd in {reglist}:<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Rd = [addr]<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;update address based on {type} }}
 {{inst|mn=LDR  |col 1=LDR<cond>{B} Rd, [Rn {, #imm}]{!}   |col 2=Load register immed |col 3 = Rd = [Rn + imm]<br>If !: Rn = Rn + imm}}
-{{inst|mn=LDR  |col 1=LDR<cond>{B} Rd,  [Rn, Rm {, <shift>}]{!}  |col 2=Load register     |col 3 = Rd = [Rn + {shifted Rm}<br>If !: Rn = Rn + {shifted Rm}]}}
+{{inst|mn=LDR  |col 1=LDR<cond>{B} Rd,  [Rn, Rm {, <shift>}]{!}  |col 2=Load register     |col 3 = Rd = [Rn + {shifted Rm}]<br>If !: Rn = Rn + {shifted Rm}]}}
 {{inst|mn=LDR  |col 1=LDR<cond>{B}{T} Rd,  [Rn], #imm  |col 2=Load register, post index     |col 3 = Rd = [Rn]<br>Rn = Rn + imm}}
 {{inst|mn=LDR  |col 1=LDR<cond>{B}{T} Rd,  [Rn], Rm {, <shift>}  |col 2=Load register, post index     |col 3 = Rd = [Rn]<br>Rn = Rn + {shifted Rm} }}
 {{inst|cols=5|section=<span id="store_instructions">'''Store Instructions'''</span>}}
-{{inst|mn=STR   |col 1=STR{cond} Rd, address     |col 2=Store Word                       |col 3 = [address] = Rd}}
+{{inst|mn=STM  |col 1=STM<cond><type> Rn{!}, <reglist>{^} |col 2= Store multiple |col 3 = addr = Rn<br>for each Rd in {reglist}:<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[addr] = Rd<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;update address based on {type} }}
-{{inst|mn=STRT  |col 1=STRT{cond} Rd, address    |col 2=Store Word, User Mode Privilege  |col 3 = [address] = Rd}}
+{{inst|mn=STR  |col 1=STR<cond>{B} Rd, [Rn {, #imm}]{!}   |col 2=Store register immed |col 3 = [Rn + imm] = Rd<br>If !: Rn = Rn + imm}}
-{{inst|mn=STRB  |col 1=STRB{cond} Rd, address    |col 2=Store Byte                       |col 3 = [address][7:0] = Rd[7:0]}}
+{{inst|mn=STR  |col 1=STR<cond>{B} Rd,  [Rn, Rm {, <shift>}]{!}  |col 2=Store register     |col 3 = [Rn + {shifted Rm}] = Rd<br>If !: Rn = Rn + {shifted Rm}]}}
-{{inst|mn=STRBT |col 1=STRBT{cond} Rd, address   |col 2=Store Byte, User Mode Privilege  |col 3 = [address][7:0] = Rd[7:0]}}
+{{inst|mn=STR  |col 1=STR<cond>{B}{T} Rd,  [Rn], #imm  |col 2=Store register, post index     |col 3 = [Rn] = Rd<br>Rn = Rn + imm}}
-{{inst|mn=STM   |col 1=STM{cond}{type} Rn[!], {reglist} |col 2= Store Multiple |col 3 = addr = Rn<br>for each Rd in {reglist}:<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[addr] = Rd<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addr += {type} }}
+{{inst|mn=STR  |col 1=STR<cond>{B}{T} Rd,  [Rn], Rm {, <shift>}  |col 2=Store register, post index     |col 3 = [Rn] = Rd<br>Rn = Rn + {shifted Rm} }}
-{{inst|mn=STM   |col 1=STM{cond}{type} Rn[!], {reglist}^ |col 2= Store Multiple, User Mode Privilege |col 3 = addr = Rn<br>for each Rd in {reglist}:<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[addr]
- = Rd<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Rn += {type} }}
 {{inst|cols=5|section=<span id="arithmetic_instructions">'''Arithmetic Instructions'''</span>}}
-{{inst|mn=ADC |col 1=ADC<cond>{S} Rd, Rn, #imm           |col 2=Add and carry immed  |col 3 =Rd = Rn + imm + C}}
+{{inst|mn=ADC |col 1=ADC<cond>{S} Rd, Rn, #imm           |col 2=Add and carry immed               |col 3 =Rd = Rn + imm + C}}
-{{inst|mn=ADC |col 1=ADC<cond>{S} Rd, Rn, Rm{, <shift>}  |col 2=Add and carry        |col 3 =Rd = Rn + {shifted Rm} + C}}
+{{inst|mn=ADC |col 1=ADC<cond>{S} Rd, Rn, Rm{, <shift>}  |col 2=Add and carry                     |col 3 =Rd = Rn + {shifted Rm} + C}}
-{{inst|mn=ADD |col 1=ADD<cond>S Rd, Rn, #imm             |col 2=Add immed            |col 3 =Rd = Rn + imm}}
+{{inst|mn=ADD |col 1=ADD<cond>S Rd, Rn, #imm             |col 2=Add immed                         |col 3 =Rd = Rn + imm}}
-{{inst|mn=ADD |col 1=ADD<cond>S Rd, Rn, Rm{, <shift>}    |col 2=Add                  |col 3 =Rd = Rn + {shifted Rm} }}
+{{inst|mn=ADD |col 1=ADD<cond>S Rd, Rn, Rm{, <shift>}    |col 2=Add                               |col 3 =Rd = Rn + {shifted Rm} }}
+{{inst|mn=RSB |col 1=RSB<cond>S Rd, Rn, #imm             |col 2=Reverse subtract immed            |col 3 =Rd = imm - Rn}}
+{{inst|mn=RSB |col 1=RSB<cond>S Rd, Rn, Rm{, <shift>}    |col 2=Reverse subtract                  |col 3 =Rd = {shifted Rm} - Rn }}
+{{inst|mn=RSC |col 1=RSB<cond>S Rd, Rn, #imm             |col 2=Reverse subtract with carry immed |col 3 =Rd = imm - Rn - {{l|not|C}}}}
+{{inst|mn=RSC |col 1=RSB<cond>S Rd, Rn, Rm{, <shift>}    |col 2=Reverse subtract with carry       |col 3 =Rd = {shifted Rm} - Rn - {{l|not|C}}}}
+{{inst|mn=SBC |col 1=SBC<cond>{S} Rd, Rn, #imm           |col 2=Subtract with carry immed         |col 3 =Rd = Rn - imm - {{l|not|C}}}}
+{{inst|mn=SBC |col 1=SBC<cond>{S} Rd, Rn, Rm{, <shift>}  |col 2=Subtract with carry               |col 3 =Rd = Rn - {shifted Rm} - {{l|not|C}}}}
 {{inst|cols=5|section=<span id="logical_instructions">'''Logical Instructions'''</span>}}

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Revision as of 18:23, 27 June 2017

Overview

Registers

Instruction Listing