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Difference between revisions of "arm/armv1"
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(→‎Instruction Listing)
(→‎Instruction Listing)
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{{inst|cols=5|section=<span id="logical_instructions">'''Logical Instructions'''</span>}}
 
{{inst|cols=5|section=<span id="logical_instructions">'''Logical Instructions'''</span>}}
−
{{inst|mn=AND |col 1=AND<cond>{S} Rd, Rn, #imm          |col 2=AND immed       |col 3 =Rd = {{l|and|Rn|imm}}}}
+
{{inst|mn=AND |col 1=AND<cond>{S} Rd, Rn, #imm          |col 2=AND immed         |col 3 =Rd = {{l|and|Rn|imm}}}}
−
{{inst|mn=AND |col 1=AND<cond>{S} Rd, Rn, Rm[, <shift>] |col 2=AND             |col 3 =Rd = {{l|and|Rn|{shifted Rm} }}}}
+
{{inst|mn=AND |col 1=AND<cond>{S} Rd, Rn, Rm[, <shift>] |col 2=AND               |col 3 =Rd = {{l|and|Rn|{shifted Rm} }}}}
−
{{inst|mn=BIC |col 1=BIC<cond>{S} Rd, Rn, #imm          |col 2=Bit clear immed |col 3 =Rd = {{l|and|Rn|{{l|not|imm}}}}}}
+
{{inst|mn=BIC |col 1=BIC<cond>{S} Rd, Rn, #imm          |col 2=Bit clear immed   |col 3 =Rd = {{l|and|Rn|{{l|not|imm}}}}}}
−
{{inst|mn=BIC |col 1=BIC<cond>{S} Rd, Rn, Rm[, <shift>] |col 2=Bit clear       |col 3 =Rd = {{l|and|Rn|{{l|not|Rm}}}}}}
+
{{inst|mn=BIC |col 1=BIC<cond>{S} Rd, Rn, Rm[, <shift>] |col 2=Bit clear         |col 3 =Rd = {{l|and|Rn|{{l|not|Rm}}}}}}
 +
{{inst|mn=EOR |col 1=EOR<cond>{S} Rd, Rn, #imm          |col 2=Exclusive OR immed |col 3 =Rd = {{l|xor|Rn|imm}}}}
 +
{{inst|mn=EOR |col 1=EOR<cond>{S} Rd, Rn, Rm[, <shift>] |col 2=Exclusive OR      |col 3 =Rd = {{l|xor|Rn|{shifted Rm} }}}}
  
 
{{inst|mn=xxxxxxx  |col 1=xxxxxxxxxxxxxx    |col 2=xxxxxxxxxx                      |col 3 =xxxxxxxxxxxxxxxxx}}
 
{{inst|mn=xxxxxxx  |col 1=xxxxxxxxxxxxxx    |col 2=xxxxxxxxxx                      |col 3 =xxxxxxxxxxxxxxxxx}}
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{{inst|mn=CMN  |col 1=CMN<cond> Rn, #imm          |col 2=Compare negative immed |col 3 =CPSR flags set on (Rn + imm)}}
 
{{inst|mn=CMN  |col 1=CMN<cond> Rn, #imm          |col 2=Compare negative immed |col 3 =CPSR flags set on (Rn + imm)}}
 
{{inst|mn=CMN  |col 1=CMN<cond> Rn, Rm[, <shift>] |col 2=Compare negative      |col 3 =CPSR flags set on (Rn + {shifted Rm})}}
 
{{inst|mn=CMN  |col 1=CMN<cond> Rn, Rm[, <shift>] |col 2=Compare negative      |col 3 =CPSR flags set on (Rn + {shifted Rm})}}
 +
{{inst|mn=CMP  |col 1=CMP<cond> Rn, #imm          |col 2=Compare immed          |col 3 =CPSR flags set on (Rn - imm)}}
 +
{{inst|mn=CMP  |col 1=CMP<cond> Rn, Rm[, <shift>] |col 2=Compare                |col 3 =CPSR flags set on (Rn - {shifted Rm})}}
 
{{inst|cols=5|section=<span id="branch_instructions">'''Branch Instructions'''</span>}}
 
{{inst|cols=5|section=<span id="branch_instructions">'''Branch Instructions'''</span>}}
 
{{inst|mn=B  |col 1=B<cond> #imm |col 2=Branch relative |col 3 =PC = PC + address}}
 
{{inst|mn=B  |col 1=B<cond> #imm |col 2=Branch relative |col 3 =PC = PC + address}}

Revision as of 18:19, 27 June 2017

ARMv1 is the first ARM instruction set version. Introduced with the ARM1 on April 26 1985, the ARMv1 defines a 32-bit ISA along with 26-bit addressing space. The ARMv1 was only implemented by the ARM1 and was replaced soon after by the ARM2. Only a few hundred of those chips were ever fabricated.

Overview

The ARMv1 is a simple architecture. Each instruction is 32-bit in size and operates on two 32-bit operands. There is a program counter which is 26 bits in size allowing for an address space of up to 64 MiB of data.

Registers

There are 16 general purpose 32-bit registers. With the exception of register 15, all registers are orthogonal with no specific designated purpose.

Instruction Listing

The ARMv1 is broken down into 7 classes of instruction:

ARMv1 ISA
Mnemonic Syntax Description Action
Load Instructions
LDRLDR{cond} Rd, addressLoad WordRd = [address]
LDRTLDRT{cond} Rd, addressLoad Word, User Mode PrivilegeRd = [address]
LDRBLDRB{cond} Rd, addressLoad ByteRd = ZeroExtend([address])
LDRBTLDRBT{cond} Rd, addressLoad Byte, User Mode PrivilegeRd = ZeroExtend([address])
LDMLDM{cond}{type} Rn[!], {reglist}Load Multipleaddr = Rn
for each Rd in {reglist}:
     Rd = [addr]
     addr += {type}
LDMLDM{cond}{type} Rn[!], {reglist, PC}Load Multipleaddr = Rn
for each Rd in {reglist}:
     Rd = [addr]
     addr += {type}
R15 = [addr]
Store Instructions
STRSTR{cond} Rd, addressStore Word[address] = Rd
STRTSTRT{cond} Rd, addressStore Word, User Mode Privilege[address] = Rd
STRBSTRB{cond} Rd, addressStore Byte[address][7:0] = Rd[7:0]
STRBTSTRBT{cond} Rd, addressStore Byte, User Mode Privilege[address][7:0] = Rd[7:0]
STMSTM{cond}{type} Rn[!], {reglist}Store Multipleaddr = Rn
for each Rd in {reglist}:
     [addr] = Rd
     addr += {type}
STMSTM{cond}{type} Rn[!], {reglist}^Store Multiple, User Mode Privilegeaddr = Rn
for each Rd in {reglist}:
     [addr] = Rd
     Rn += {type}
Arithmetic Instructions
ADCADC<cond>{S} Rd, Rn, #immAdd and carry immedRd = Rn + imm + C
ADCADC<cond>{S} Rd, Rn, Rm[, <shift>]Add and carryRd = Rn + {shifted Rm} + C
ADDADD<cond>S Rd, Rn, #immAdd immedRd = Rn + imm
ADDADD<cond>S Rd, Rn, Rm[, <shift>]AddRd = Rn + {shifted Rm}
Logical Instructions
ANDAND<cond>{S} Rd, Rn, #immAND immedRd = Rn · imm
ANDAND<cond>{S} Rd, Rn, Rm[, <shift>]ANDRd = Rn · {shifted Rm}
BICBIC<cond>{S} Rd, Rn, #immBit clear immedRd = Rn · ¬imm
BICBIC<cond>{S} Rd, Rn, Rm[, <shift>]Bit clearRd = Rn · ¬Rm
EOREOR<cond>{S} Rd, Rn, #immExclusive OR immedRd = Rn ⊕ imm
EOREOR<cond>{S} Rd, Rn, Rm[, <shift>]Exclusive ORRd = Rn ⊕ {shifted Rm}
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Comparison Instructions
CMNCMN<cond> Rn, #immCompare negative immedCPSR flags set on (Rn + imm)
CMNCMN<cond> Rn, Rm[, <shift>]Compare negativeCPSR flags set on (Rn + {shifted Rm})
CMPCMP<cond> Rn, #immCompare immedCPSR flags set on (Rn - imm)
CMPCMP<cond> Rn, Rm[, <shift>]CompareCPSR flags set on (Rn - {shifted Rm})
Branch Instructions
BB<cond> #immBranch relativePC = PC + address
BLBL<cond> #immBranch and link relativeLR = RET
PC = PC + address
Miscellaneous Instructions
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