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Difference between revisions of "arm/armv1"
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(initial listing)
(starting to add the info)
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* [[#load_instructions|Load Instructions]]
 
* [[#load_instructions|Load Instructions]]
 
* [[#store_instructions|Store Instructions]]
 
* [[#store_instructions|Store Instructions]]
 +
* [[#arithmetic_instructions|Arithmetic Instructions]]
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* [[#logical_instructions|Logical Instructions]]
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* [[#comparison_instructions|Comparison Instructions]]
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* [[#branch_instructions|Branch Instructions]]
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* [[#miscellaneous_instructions|Miscellaneous Instructions]]
  
 
{{isa
 
{{isa
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{{inst|mn=STM  |col 1=STM{cond}{type} Rn[!], {reglist}^ |col 2= Store Multiple, User Mode Privilege |col 3 = addr = Rn<br>for each Rd in {reglist}:<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[addr]
 
{{inst|mn=STM  |col 1=STM{cond}{type} Rn[!], {reglist}^ |col 2= Store Multiple, User Mode Privilege |col 3 = addr = Rn<br>for each Rd in {reglist}:<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[addr]
 
  = Rd<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Rn += {type} }}
 
  = Rd<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Rn += {type} }}
 +
 +
{{inst|cols=5|section=<span id="arithmetic_instructions">'''Arithmetic Instructions'''</span>}}
 +
{{inst|mn=ADC |col 1=ADC<cond>{S} Rd, Rn, #imm          |col 2=Add and carry immed  |col 3 =Rd = Rn + immd + C}}
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{{inst|mn=ADC |col 1=ADC<cond>{S} Rd, Rn, Rm[, <shift>]  |col 2=Add and carry        |col 3 =Rd = Rn + {shifted Rm} + C}}
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{{inst|mn=ADD |col 1=ADD<cond>S Rd, Rn, #imm            |col 2=Add immed            |col 3 =Rd = Rn + immd}}
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{{inst|mn=ADD |col 1=ADD<cond>S Rd, Rn, Rm[, <shift>]    |col 2=Add                  |col 3 =Rd = Rn + {shifted Rm} }}
 +
 +
{{inst|cols=5|section=<span id="logical_instructions">'''Logical Instructions'''</span>}}
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{{inst|mn=AND |col 1=AND<cond>{S} Rd, Rn, #imm          |col 2=AND immed |col 3 =Rd = {{l|and|Rn|immd}}}}
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{{inst|mn=AND |col 1=AND<cond>{S} Rd, Rn, Rm[, <shift>] |col 2=AND      |col 3 =Rd = {{l|and|Rn|{shifted Rm} }}}}
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 +
{{inst|mn=xxxxxxx  |col 1=xxxxxxxxxxxxxx    |col 2=xxxxxxxxxx                      |col 3 =xxxxxxxxxxxxxxxxx}}
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{{inst|mn=xxxxxxx  |col 1=xxxxxxxxxxxxxx    |col 2=xxxxxxxxxx                      |col 3 =xxxxxxxxxxxxxxxxx}}
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{{inst|mn=xxxxxxx  |col 1=xxxxxxxxxxxxxx    |col 2=xxxxxxxxxx                      |col 3 =xxxxxxxxxxxxxxxxx}}
 +
{{inst|mn=xxxxxxx  |col 1=xxxxxxxxxxxxxx    |col 2=xxxxxxxxxx                      |col 3 =xxxxxxxxxxxxxxxxx}}
 +
{{inst|mn=xxxxxxx  |col 1=xxxxxxxxxxxxxx    |col 2=xxxxxxxxxx                      |col 3 =xxxxxxxxxxxxxxxxx}}
 +
{{inst|mn=xxxxxxx  |col 1=xxxxxxxxxxxxxx    |col 2=xxxxxxxxxx                      |col 3 =xxxxxxxxxxxxxxxxx}}
 +
{{inst|mn=xxxxxxx  |col 1=xxxxxxxxxxxxxx    |col 2=xxxxxxxxxx                      |col 3 =xxxxxxxxxxxxxxxxx}}
 +
{{inst|mn=xxxxxxx  |col 1=xxxxxxxxxxxxxx    |col 2=xxxxxxxxxx                      |col 3 =xxxxxxxxxxxxxxxxx}}
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{{inst|mn=xxxxxxx  |col 1=xxxxxxxxxxxxxx    |col 2=xxxxxxxxxx                      |col 3 =xxxxxxxxxxxxxxxxx}}
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 +
{{inst|cols=5|section=<span id="comparison_instructions">'''Comparison Instructions'''</span>}}
 +
{{inst|cols=5|section=<span id="branch_instructions">'''Branch Instructions'''</span>}}
 +
{{inst|cols=5|section=<span id="miscellaneous_instructions">'''Miscellaneous Instructions'''</span>}}
  
 
}}
 
}}

Revision as of 16:54, 27 June 2017

ARMv1 is the first ARM instruction set version. Introduced with the ARM1 on April 26 1985, the ARMv1 defines a 32-bit ISA along with 26-bit addressing space. The ARMv1 was only implemented by the ARM1 and was replaced soon after by the ARM2. Only a few hundred of those chips were ever fabricated.

Overview

The ARMv1 is a simple architecture. Each instruction is 32-bit in size and operates on two 32-bit operands. There is a program counter which is 26 bits in size allowing for an address space of up to 64 MiB of data.

Registers

There are 16 general purpose 32-bit registers. With the exception of register 15, all registers are orthogonal with no specific designated purpose.

Instruction Listing

The ARMv1 is broken down into 2 classes of instruction:

ARMv1 ISA
Mnemonic Syntax Description Action
Load Instructions
LDRLDR{cond} Rd, addressLoad WordRd = [address]
LDRTLDRT{cond} Rd, addressLoad Word, User Mode PrivilegeRd = [address]
LDRBLDRB{cond} Rd, addressLoad ByteRd = ZeroExtend([address])
LDRBTLDRBT{cond} Rd, addressLoad Byte, User Mode PrivilegeRd = ZeroExtend([address])
LDMLDM{cond}{type} Rn[!], {reglist}Load Multipleaddr = Rn
for each Rd in {reglist}:
     Rd = [addr]
     addr += {type}
LDMLDM{cond}{type} Rn[!], {reglist, PC}Load Multipleaddr = Rn
for each Rd in {reglist}:
     Rd = [addr]
     addr += {type}
R15 = [addr]
Store Instructions
STRSTR{cond} Rd, addressStore Word[address] = Rd
STRTSTRT{cond} Rd, addressStore Word, User Mode Privilege[address] = Rd
STRBSTRB{cond} Rd, addressStore Byte[address][7:0] = Rd[7:0]
STRBTSTRBT{cond} Rd, addressStore Byte, User Mode Privilege[address][7:0] = Rd[7:0]
STMSTM{cond}{type} Rn[!], {reglist}Store Multipleaddr = Rn
for each Rd in {reglist}:
     [addr] = Rd
     addr += {type}
STMSTM{cond}{type} Rn[!], {reglist}^Store Multiple, User Mode Privilegeaddr = Rn
for each Rd in {reglist}:
     [addr] = Rd
     Rn += {type}
Arithmetic Instructions
ADCADC<cond>{S} Rd, Rn, #immAdd and carry immedRd = Rn + immd + C
ADCADC<cond>{S} Rd, Rn, Rm[, <shift>]Add and carryRd = Rn + {shifted Rm} + C
ADDADD<cond>S Rd, Rn, #immAdd immedRd = Rn + immd
ADDADD<cond>S Rd, Rn, Rm[, <shift>]AddRd = Rn + {shifted Rm}
Logical Instructions
ANDAND<cond>{S} Rd, Rn, #immAND immedRd = Rn · immd
ANDAND<cond>{S} Rd, Rn, Rm[, <shift>]ANDRd = Rn · {shifted Rm}
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Comparison Instructions
Branch Instructions
Miscellaneous Instructions
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