Semiconductor & Computer Engineering
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| − | '''ARM 26-bit architectures''' refers to a number of early [[ARM]] ISA versions and [[microarchitectures]] that implement them that only implement a 26-bit address space. Those architectures have been long obsolete and are no longer supported or implemented. 26-bit ARM ISAs are known as {{arm|ARMv1}}, {{arm|ARMv2}}, and {{arm|ARMv2a}} | + | '''ARM 26-bit architectures''' refers to a number of early [[ARM]] ISA versions and [[microarchitectures]] that implement them that only implement a 26-bit address space. Those architectures have been long obsolete and are no longer supported or implemented. |
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| + | == Overview == | ||
| + | In the first few versions of [[ARM]], the [[Program Counter]] was only 26 bits, allowing it to access 64 MiB of memory. The high 6 bits were actually used for the {{arm|Processor Status Register}}. With the introduction of the {{arm|ARMv3}}, the ISA implements a 32-bit address space. ARMv3 consequently introduced a compatibility mode to support the older architectures (except for {{arm|ARMv3G}}). With the introduction of {{arm|ARMv4}}, the mode became optional on all non-T variants. {{arm|ARMv5}} dropped 26-bit compatibility entirely. | ||
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| + | === Major Differences === | ||
| + | The most major difference is in the [[Program Counter]] which only implements a 24-bit program counter in {{arm|R15}}. This allows for an address space of only up to 64 MiB (note that all instructions are {{arm|Word}}-aligned, therefore the two low bits are always zero; <code>2<sup>24</sup> << 2</code>). Any memory access attempt beyond the <math>2^{26}-1</math> byte will raise a memory access exception. On the {{arm|32-bit architectures}}, the program counter was extended to 30 bits, allowing the full 4 GiB address space to be accessible. Because addresses are only 26 bits there were no restrictions on {{arm|branches}} wrapping around either past ''0x3FFFFFF'' or backwards past 0x0000000. This would lead to 26-bit architectures having different target address than they would on a 32-bit ARM architecture. Consequently, <code>B</code> and <code>BL</code> signed 24-bit offsets can branch to any address. | ||
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| + | The 26-bit architectures do not have a {{arm|CPSR}} or any {{arm|SPSR}}s. and only the four original modes are supported: <code>User</code>, <code>FIQ</code>, <code>IRQ</code>, and <code>Supervisor</code>. The remaining bits in the program counter are used for the condition flags (N, Z, C, and V), interrupt disable flags (I and F), and the two processor mode bits (M1 and M0). This had the effect of being able to save the process status across subroutine calls and without adding any additional instructions or overhead (e.g. special entry and exit sequence). | ||
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| + | == 26-bit ARM Architectures and implementations == | ||
| + | * 26-bit ARM ISAs are known as {{arm|ARMv1}}, {{arm|ARMv2}}, and {{arm|ARMv2a}} | ||
| + | * Implementations: {{armh|ARM1}}, {{armh|ARM2}}, {{armh|ARM3}}, and the {{armh|ARM250}}. | ||
Revision as of 23:28, 25 June 2017
ARM 26-bit architectures refers to a number of early ARM ISA versions and microarchitectures that implement them that only implement a 26-bit address space. Those architectures have been long obsolete and are no longer supported or implemented.
Overview
In the first few versions of ARM, the Program Counter was only 26 bits, allowing it to access 64 MiB of memory. The high 6 bits were actually used for the Processor Status Register. With the introduction of the ARMv3, the ISA implements a 32-bit address space. ARMv3 consequently introduced a compatibility mode to support the older architectures (except for ARMv3G). With the introduction of ARMv4, the mode became optional on all non-T variants. ARMv5 dropped 26-bit compatibility entirely.
Major Differences
The most major difference is in the Program Counter which only implements a 24-bit program counter in R15. This allows for an address space of only up to 64 MiB (note that all instructions are Word-aligned, therefore the two low bits are always zero; 224 << 2). Any memory access attempt beyond the byte will raise a memory access exception. On the 32-bit architectures, the program counter was extended to 30 bits, allowing the full 4 GiB address space to be accessible. Because addresses are only 26 bits there were no restrictions on branches wrapping around either past 0x3FFFFFF or backwards past 0x0000000. This would lead to 26-bit architectures having different target address than they would on a 32-bit ARM architecture. Consequently, B and BL signed 24-bit offsets can branch to any address.
The 26-bit architectures do not have a CPSR or any SPSRs. and only the four original modes are supported: User, FIQ, IRQ, and Supervisor. The remaining bits in the program counter are used for the condition flags (N, Z, C, and V), interrupt disable flags (I and F), and the two processor mode bits (M1 and M0). This had the effect of being able to save the process status across subroutine calls and without adding any additional instructions or overhead (e.g. special entry and exit sequence).