From WikiChip
Difference between revisions of "cavium/octeon plus/cn5734-600bg1217-sp"
m (Bot: Automated text replacement (-\| electrical += Yes +)) |
m (Bot: corrected param) |
||
Line 10: | Line 10: | ||
| model number = CN5734-600 SP | | model number = CN5734-600 SP | ||
| part number = CN5734-600BG1217-SP | | part number = CN5734-600BG1217-SP | ||
− | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| market = Storage | | market = Storage | ||
| first announced = Jun 26, 2007 | | first announced = Jun 26, 2007 |
Revision as of 17:03, 30 June 2017
Template:mpu CN5734-600 SP is a 64-bit hexa-core MIPS storage processor (SP) designed by Cavium and introduced in 2007. This processor, which incorporates six cnMIPS cores, operates at 600 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, networking, TCP & QoS acceleration.
Contents
Cache
- Main article: cnMIPS § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||
|
Memory controller
Integrated Memory Controller
|
||||||||||||||
|
Expansions
Expansion Options
|
||||||||||||
|
Networking
Interface options:
- 8-lanes PCIe + 8-lanes PCIe
- 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
- 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]
Networking
|
||||||
|
Hardware Accelerators
[Edit/Modify Accelerators Info]
Hardware Accelerators
|
||||||||||||||||||
|
Block diagram
Datasheet
Facts about "CN5734-600 SP - Cavium"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN5734-600 SP - Cavium#io + |
has ecc memory support | true + |
has hardware accelerators for data compression | true + |
has hardware accelerators for data decompression | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for tcp packet processing | true + |
has hardware raid 5 support | true + |
has hardware raid 6 support | true + |
l1$ size | 288 KiB (294,912 B, 0.281 MiB) + |
l1d$ size | 96 KiB (98,304 B, 0.0938 MiB) + |
l1i$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 8 + |
supported memory type | DDR2-800 + |