From WikiChip
Difference between revisions of "ambric/am2000/am2024"
m (Bot: corrected mem) |
m (Bot: corrected mem) |
||
Line 40: | Line 40: | ||
| thread count = | | thread count = | ||
| max cpus = | | max cpus = | ||
− | | max memory = 4 | + | | max memory = 4 GiB |
| electrical = | | electrical = |
Revision as of 18:37, 23 June 2017
Template:mpu Am2024 was an MPPA introduced in late 2006 by Ambric. This model was made of 24 Brics arranged as a grid, making up a total of 192 32-bit RICS-like cores operating asynchronously at 1-333 MHz.
Architecture
- Main article: Am2000 § Architecture
The Am2024 is made of 24 homogeneous 'Brics' laid out in a grid to form 192 cores and 192 RAM units.
General layout:
- 24x Brics
Cache
The Am2035 contains 24 Brics, each with its own RAM Unit (RU) of 13 kB of SRAM for a total of 312 kB of SRAM.
Memory controller
Integrated Memory Controller | |
Type | DDR2-400 |
Controllers | 2 |
Channels | 1 |
Max memory | 4 GiB |
Expansions
- PCIe
- JTAG
- GPIO @ 100 MHz
- serial flash