Semiconductor & Computer Engineering
(→Expansions) |
(→Cache) |
||
| Line 82: | Line 82: | ||
== Cache == | == Cache == | ||
| − | PEZY-1's cache is separate from the {{armh|ARM926}}'s cache which has an L1$ of | + | PEZY-1's cache is separate from the {{armh|ARM926}}'s cache which has an L1$ of 16 KiB (2x) and no L2$. |
| − | {{cache | + | {{cache size |
| − | |l1 cache=128 KiB | + | |l1 cache=128 MiB |
| + | |l1i cache=64 KiB | ||
| + | |l1d cache=64 KiB | ||
|l2 cache=1 MiB | |l2 cache=1 MiB | ||
| − | |||
| − | |||
}} | }} | ||
Revision as of 05:39, 23 June 2017
Template:mpu PEZY-1 was a first generation many-core microprocessor developed by PEZY in 2012. PEZY-1 contains 2 ARM926 cores (ARMv5TEJ) along with 512 simpler RISC cores. Operating at 533 MHz, the processor is said to have peach performance of 533 GFLOPS (single-precision) and 266 GFLOPS (double-precision). PEZY-1 was designed using 220 million gates and manufactured on TSMC's 40 nm process.
The PEZY-1 is used for image processing devices and various medical instruments. In 2014 PEZY introduced their second generation many-core processor, the PEZY-SC, with twice as many cores.
Cache
PEZY-1's cache is separate from the ARM926's cache which has an L1$ of 16 KiB (2x) and no L2$.
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||
|
|||||||||||||||||||||||||
Memory controller
 |
Integrated Memory Controller
|
|||||||||||||
|
||||||||||||||
Expansions
 |
Expansion Options
|
|||||||||||
|
||||||||||||
PEZY-1 Quad PCI Board
PEZY has developed a Quad-PEZY-1 PCI board for their microprocessors which has 4 PEZY-1 for a total of 2,048 PE cores (along with 8 ARM cores). The board is equipped with 64 GB of memory for a total bandwidth of 200 GB/s. PEZY reports the total computational power for the board to be at 2.56 TFLOPS with a power consumption of 180 Watts.
Documents
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | PEZY-1 - PEZY#io + |
| has ecc memory support | true + |
| l1$ size | 131,072 KiB (134,217,728 B, 128 MiB) + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| max memory bandwidth | 39.74 GiB/s (40,693.76 MiB/s, 42.671 GB/s, 42,670.5 MB/s, 0.0388 TiB/s, 0.0427 TB/s) + |
| max memory channels | 4 + |
| max pcie lanes | 24 + |
| supported memory type | DDR3-1333 + |