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Difference between revisions of "cavium/octeon plus/cn5860-600bg1521-nsp"
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| model number = CN5860-600 NSP | | model number = CN5860-600 NSP | ||
| part number = CN5860-600BG1521-NSP | | part number = CN5860-600BG1521-NSP | ||
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| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| market = Network | | market = Network | ||
| first announced = October 9, 2006 | | first announced = October 9, 2006 |
Revision as of 18:15, 30 June 2017
Template:mpu CN5860-600 NSP is a 64-bit hexadeca-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2007. This processor, which incorporates sixteen cnMIPS cores, operates at 600 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance network services software such as encryption, RegEx, compression/decompression, and TCP acceleration.
Contents
Cache
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Networking
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Networking
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Hardware Accelerators
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Block diagram
Datasheet
Facts about "CN5860-600 NSP - Cavium"