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Difference between revisions of "dec/microarchitectures/alpha 21164"
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|isa=Alpha | |isa=Alpha | ||
Revision as of 07:03, 13 June 2017
| Edit Values | |
| Alpha 21164 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | DEC |
| Manufacturer | DEC |
| Introduction | January, 1995 |
| Process | 0.5 µm |
| Core Configs | 1 |
| Pipeline | |
| Type | Superscalar |
| OoOE | No |
| Speculative | Yes |
| Reg Renaming | No |
| Stages | 7-12 |
| Decode | 4-way |
| Instructions | |
| ISA | Alpha |
| Cache | |
| L1I Cache | 8 KiB/core direct-mapped |
| L1D Cache | 8 KiB/core direct-mapped |
| L2 Cache | 96 KiB/core 3-way set associative |
| L3 Cache | 1-64 MiB/motherboard direct-mapped |
| Succession | |
Alpha 21164 was an Alpha microarchitecture designed by DEC and introduced in 1995 as a successor to the Alpha 21064 architecture.
Facts about "Alpha 21164 - Microarchitectures - DEC"
| codename | Alpha 21164 + |
| core count | 1 + |
| designer | DEC + |
| first launched | January 1995 + |
| full page name | dec/microarchitectures/alpha 21164 + |
| instance of | microarchitecture + |
| instruction set architecture | Alpha + |
| manufacturer | DEC + |
| microarchitecture type | CPU + |
| name | Alpha 21164 + |
| pipeline stages (max) | 9 + |
| pipeline stages (min) | 7 + |
| process | 500 nm (0.5 μm, 5.0e-4 mm) + |