From WikiChip
Difference between revisions of "intel/core m/m5-6y57"
(→Features) |
|||
Line 177: | Line 177: | ||
|sse42=Yes | |sse42=Yes | ||
|sse4a=No | |sse4a=No | ||
− | |avx= | + | |avx=Yes |
− | |avx2= | + | |avx2=Yes |
|avx512=No | |avx512=No | ||
|abm=Yes | |abm=Yes | ||
Line 194: | Line 194: | ||
|f16c=Yes | |f16c=Yes | ||
|tbt1=No | |tbt1=No | ||
− | |tbt2= | + | |tbt2=Yes |
|tbmt3=No | |tbmt3=No | ||
|bpt=No | |bpt=No | ||
Line 204: | Line 204: | ||
|sba=No | |sba=No | ||
|mwt=Yes | |mwt=Yes | ||
− | |sipp= | + | |sipp=Yes |
|att=No | |att=No | ||
− | |ipt= | + | |ipt=No |
− | |tsx= | + | |tsx=Yes |
− | |txt= | + | |txt=Yes |
|ht=Yes | |ht=Yes | ||
− | |vpro= | + | |vpro=Yes |
|vtx=Yes | |vtx=Yes | ||
|vtd=Yes | |vtd=Yes | ||
|ept=Yes | |ept=Yes | ||
− | |mpx= | + | |mpx=Yes |
|sgx=Yes | |sgx=Yes | ||
|securekey=Yes | |securekey=Yes | ||
− | |osguard= | + | |osguard=Yes |
|3dnow=No | |3dnow=No | ||
|e3dnow=No | |e3dnow=No |
Revision as of 20:31, 3 June 2017
Template:mpu Core M5-6Y57 is an ultra-low power 64-bit dual-core x86 microprocessor introduced by Intel in late 2015. This MPU operates at 1.1 GHz with a max turbo frequency of 2.8 GHz. This chip, which is manufactured on a 14 nm process, is based on the Skylake microarchitecture. The Core M5-6Y57 incorporates Intel's HD Graphics 515 Gen9 GPU clocked at 300 MHz with turbo frequency of 900 MHz.
Cache
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Memory controller
Integrated Memory Controller
|
||||||||||||||
|
Expansions
Expansion Options
|
||||||||
|
Graphics
Integrated Graphics Information
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
[Edit] Skylake (Gen9) Hardware Accelerated Video Capabilities | |||||||
---|---|---|---|---|---|---|---|
Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, SHP, MHP | 5.1 | 2160p (4K) | |
JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
HEVC (H.265) | Main | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High | 3840x3840 | |||
VP8 | Unified | Unified | - | 0 | Unified | 1080p | |
VP9 | ✘ | 0 | Unified | 2160p (4K) |
Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
Drivers
Facts about "Core m5-6Y57 - Intel"